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ds07-13603-4e fujitsu semiconductor data sheet 16-bit proprietary microcontroller cmos f 2 mc-16l mb90610a series mb90611a/mb90613a n description mb90610a series includes 16-bit microcontrollers optimally usable for high-speed real-time data processing in consumer appliances and for system control of printer, cd-rom, celluar phone, copier, etc. the series uses the *f 2 mc-16l cpu which is based on the f 2 mc-16 but with enhanced high-level language and task switching instructions and additional addressing modes. the internal peripheral resources consist of a 3-channel serial port incorporating a uart function (and supporting i/o expansion serial mode), 8-channel 10-bit a/d converter, 2-channel ppg, 2-channel 16-bit reload timer, 8-channel chip select output, and 8-channel external interrupts. also, multiplexed or non-multiplexed operation can be selected for the address/data bus. *: f 2 mc is an abbreviation for fujitsu flexible microcontroller. n features ?f 2 mc-16l cpu ? minimum instruction execution time: 62.5 ns/4 mhz oscillation (uses pll clock multiplication), maximum multiplier = 4 ? instruction set optimized for controller applications upward object code compatibility with f 2 mc-16 (h) wide range of data types (bit/byte/word/long word) improved instruction cycles provide increased speed additional addressing modes: 23 modes high code efficiency access methods (bank access/linear pointer) enhanced multiplication and division instructions (signed instructions added) high precision operations are enhanced by use of a 32-bit accumulator extended intelligent i/o service (access area extended to 64 kbytes) maximum memory space: 16 mbytes (continued) n pac k ag e 100-pin plastic lqfp (fpt-100p-m05) 100-pin plastic qfp (fpt-100p-m06)
2 mb90610a series (continued) ? enhanced high level language (c)/multitasking support instructions use of a system stack pointer enhanced pointer indirect instructions barrel shift instructions stack check function ? improved execution speed: four byte instruction queue ? powerful interrupt function ? automatic data transfer function (does not use instructions) internal peripherals ? ram: 1 kbyte (mb90611a) 3 kbytes (mb90613a) ? general purpose ports 8, 16-bit data bus, multiplexed mode : 57 ports max. 16-bit non-multiplexed mode : 41 ports max. 8-bit non-multiplexed mode : 49 ports max. ? uart (sci): 3 channels for either asynchronous or clocked serial transfer (i/o expansion serial) ? a/d converter: 8 channels (10-bit) 8-bit conversion mode also available ? ppg (programmable pulse generator): 2 channels ? 16-bit reload timer: 2 channels ? chip select output: 8 channels ? external interrupts: 8 channels ? 18-bit timebase timer watchdog timer function ? pll clock multiplier function ? cpu intermittent operation function ? various standby modes ? lqfp-100/qfp-100 package ?cmos technology
mb90610a series 3 n product lineup mb90611a mb90613a classification mask rom rom size ram size 1 kbyte 3 kbytes cpu functions number of basic instructions : 340 instruction bit length : 8/16 bits instruction length : 1 to 7 bytes data bit length : 1/4/8/16/32 bits minimum instruction execution time : 62.5 ns/4 mhz (pll multiplier = 4) interrupt processing time : 1000 ns/16 mhz (minimum) ports i/o ports (cmos/ttl) : 33 (31 cmos/2 ttl) (n-channel open drain): 8 (16-bit non-multiplex mode) to t a l : 4 1 packages fpt-100p-m05 fpt-100p-m06 uart (sci) three internal uarts full-duplex, double-buffered selectable clock synchronous or asynchronous operation built-in dedicated baud rate generator a/d converter 10-bit 8 channels a/d conversion time : 6.13 m s (98 machine cycles/16 mhz machine clock, includes sample and hold time) triggers : software, external, or multi-function timer output (rt0) activation can be selected. activation modes : single, scan (continuous conversion of multiple channels), continuous (continuous conversion of one channel), and stop (scan mode with synchronized conversion start) ppg 2 8-bit ppg outputs (1 channel ppg output in 16-bit mode) 16-bit reload timer 16-bit reload timer operation (selectable toggle output, one-shot output) (selectable count clock: 0.125 m s, 0.5 m s, or 2.0 m s for a 16 mhz machine cycle) selectable event count function, 2 internal channels chip select 8 outputs external interrupts 8 inputs external interrupt mode (interrupts can be generated from four different types of request signal) pll function selectable multiplier: 1/2/3/4 (set a multiplier that does not exceed the assured operation frequency range.) other part no. parameter
4 mb90610a series n pin assignment 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 rst p54/wrh p53/hrq p52/hak p51/rdy p50/clk pa7/cs7 pa6/cs6 pa5/cs5 pa4/cs4 pa3/cs3 pa2/cs2 pa1/cs1 cs0 p95/sck2 p94/sot2 p93/sin2 p92/sck1 p91/sot1 p90/sin1 p86/sck0 p85/sot0 p84/sin0 p83/tot1 p82/tot0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 p22/a02 p23/a03 p24/a04 p25/a05 p26/a06 p27/a07 p30/a08 p31/a09 v ss p32/a10 p33/a11 p34/a12 p35/a13 p36/a14 p37/a15 p40/a16 p41/a17 p42/a18 p43/a19 p44/a20 v cc p45/a21 p46/a22 p47/a23 p70/int0 p71/int1 p72/int2 p73/int3 p74/int4/ppg0 p75/int5/ppg1 p76/int6/atg av cc avrh avrl av ss p60/an0 p61/an1 p62/an2 p63/an3 v ss p64/an4 p65/an5 p66/an6 p67/an7 p80/int7/tin0 p81/tin1 md0 md1 md2 hst p21/a01 p20/a00 p17/d15/ad15 p16/d14/ad14 p15/d13/ad13 p14/d12/ad12 p13/d11/ad11 p12/d10/ad10 p11/d09/ad09 p10/d08/ad08 d07/ad07 d06/ad06 d05/ad05 d04/ad04 d03/ad03 d02/ad02 d01/ad01 d00/ad00 v cc x1 x0 v ss ale rd p55/wrl (top view) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 (fpt-100p-m05)
mb90610a series 5 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ale rd p55/wrl rst p54/wrh p53/hrq p52/hak p51/rdy p50/clk pa7/cs7 pa6/cs6 pa5/cs5 pa4/cs4 pa3/cs3 pa2/cs2 pa1/cs1 cs0 p95/sck2 p94/sot2 p93/sin2 p92/sck1 p91/sot1 p90/sin1 p86/sck0 p85/sot0 p84/sin0 p83/tot1 p82/tot0 hst md2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p20/a00 p21/a01 p22/a02 p23/a03 p24/a04 p25/a05 p26/a06 p27/a07 p30/a08 p31/a09 v ss p32/a10 p33/a11 p34/a12 p35/a13 p36/a14 p37/a15 p40/a16 p41/a17 p42/a18 p43/a19 p44/a20 v cc p45/a21 p46/a22 p47/a23 p70/int0 p71/int1 p72/int2 p73/int3 p74/int4/ppg0 p75/int5/ppg1 p76/int6/atg av cc avrh avrl av ss p60/an0 p61/an1 p62/an2 p63/an3 v ss p64/an4 p65/an5 p66/an6 p67/an7 p80/int7/tin0 p81/tin1 md0 md1 p17/d15/ad15 p16/d14/ad14 p15/d13/ad13 p14/d12/ad12 p13/d11/ad11 p12/d10/ad10 p11/d09/ad09 p10/d08/ad08 d07/ad07 d06/ad06 d05/ad05 d04/ad04 d03/ad03 d02/ad02 d01/ad01 d00/ad00 v cc x1 x0 v ss (top view) 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 (fpt-100p-m06)
6 mb90610a series n pin description (continued) *1: fpt-100p-m05 *2: fpt-100p-m06 pin no. pin name circuit type function lqfp* 1 qfp* 2 80 81 82 83 x0 x1 a (oscillator) crystal oscillator pins 83 to 90 85 to 92 d00 to d07 k (ttl) in non-multiplex mode, the i/o pins for the lower 8 bits of the external data bus. ad00 to ad07 in multiplexed mode, the i/o pins for the lower 8 bits of the external address/data bus. 91 to 98 93 to 100 p10 to p17 k (ttl) general purpose i/o ports this applies in non-multiplexed mode with an 8-bit external data bus. p08 to d15 in non-multiplexed mode, the i/o pins for the upper 8 bits of the external data bus this applies when using a 16-bit external data bus. ad08 to ad15 in multiplexed mode, the i/o pins for the upper 8 bits of the external address/data bus. 99 100 1 to 6 1 to 8 p20 to p27 b (cmos) general purpose i/o ports this applies in multiplexed mode. a00 to a07 in non-multiplexed mode, the output pins for the lower 8 bits of the external address bus. 7 8 10 to 15 9 10 12 to 17 p30 to p37 b (cmos) general purpose i/o ports this applies in multiplexed mode. a08 to a15 in non-multiplexed mode, the output pins for the upper 8 bits of the external address bus. 16 to 20 22 to 24 18 to 22 24 to 26 p40 to p47 b (cmos) general purpose i/o ports this applies when the upper address control register specifies port operation. a16 to a23 the output pins for a16 to 23 of the external address bus this applies when the upper address control register specifies address operation. 25 to 28 27 to 30 p70 to p73 h (cmos/h) general purpose i/o ports this applies in all cases. int0 to int3 external interrupt request input pins as the inputs operate continuously when external interrupts are enabled, output to the pins from other functions must be stopped unless done intentionally.
mb90610a series 7 (continued) *1: fpt-100p-m05 *2: fpt-100p-m06 pin no. pin name circuit type function lqfp* 1 qfp* 2 29 30 31 32 p74, p75 h (cmos/h) general purpose i/o ports this applies when the waveform outputs for ppg timers 0 to 1 are disabled. int4, int5 external interrupt request input pins as the inputs operate continuously when external interrupts are enabled, output to the pins from other functions must be stopped unless done intentionally. ppg0, ppg1 output pins for ppg timers 0 to 1 this applies when the waveform outputs for ppg timers 0 to 1 are enabled. 31 33 p76 h (cmos/h) general purpose i/o port this applies in all cases. int6 h (cmos/h) external interrupt request input pin as the input operates continuously when the external interrupt is enabled, output to the pin from other functions must be stopped unless done intentionally. at g trigger input pin for the a/d converter as the input operates continuously when the a/d converter inputs are operating, output to the pin from other functions must be stopped unless done intentionally. 32 34 av cc power supply power supply for the analog circuits do not switch this power supply on/off unless a voltage greater than av cc is applied to v cc . 33 35 avrh power supply analog circuit reference voltage input do not switch the voltage to this pin on/off unless a voltage greater than avrh is applied to av cc . 34 36 avrl power supply analog circuit reference voltage input 35 37 av ss power supply ground level for the analog circuits 36 to 39 41 to 44 38 to 41 43 to 46 p60 to p67 c (ad) open-drain output ports this applies when port operation is specified in the analog input enable register. an0 to an7 analog input pins for the a/d converter this applies when analog input mode operation is specified in the analog input enable register. 45 47 p80 h (cmos/h) general purpose i/o port this applies in all cases. int7 external interrupt request input pin as the input operates continuously when the external interrupt is enabled, output to the pin from other functions must be stopped unless done intentionally. tin0 event input pin for reload timer 0 as the input operates continuously when the reload timer is set to input operation, output to the pin from other functions must be stopped unless done intentionally.
8 mb90610a series (continued) *1: fpt-100p-m05 *2: fpt-100p-m06 pin no. pin name circuit type function lqfp* 1 qfp* 2 46 48 p81 d (cmos/h) general purpose i/o port this applies in all cases. tin1 event input pin for reload timer 1 as the input operates continuously when the reload timer is set to input operation, output to the pin from other functions must be stopped unless done intentionally. 47, 48 49, 50 md0, md1 e (cmos/h) input pins for specifying an oprating mode connect directly to v cc or v ss . 49 51 md2 m (cmos/h) input pins for specifying an oprating mode connect directly to v cc or v ss . 50 52 hst f (cmos/h) hardware standby input pin 51, 52 53, 54 p82, p83 d (cmos/h) general purpose i/o ports this applies when output is disabled for reload timers 0 to 1. tot0, tot1 output pins for reload timers 0 to 1 this applies when output is enabled for reload timers 0 to 1. 53 55 p84 d (cmos/h) general purpose i/o port this applies in all cases. sin0 serial data input pin for uart0 as the input operates continuously when uart0 is set to input operation, output to the pin from other functions must be stopped unless done intentionally. 54 56 p85 d (cmos/h) general purpose i/o port this applies when serial data output is disabled for uart0. sot0 serial data output pin for uart0 this applies when serial data output is enabled for uart0. 55 57 p86 d (cmos/h) general purpose i/o port this applies when the uart0 clock output is disabled. sck0 clock i/o pin for uart0 this applies when the uart0 clock output is enabled. as the input operates continuously when uart0 is set to input operation, output to the pin from other functions must be stopped unless done intentionally. 56 58 p90 d (cmos/h) general purpose i/o port this applies in all cases. sin1 serial data input pin for uart1 as the input operates continuously when uart1 is set to input operation, output to the pin from other functions must be stopped unless done intentionally.
mb90610a series 9 (continued) *1: fpt-100p-m05 *2: fpt-100p-m06 pin no. pin name circuit type function lqfp* 1 qfp* 2 57 59 p91 d (cmos/h) general purpose i/o port this applies when serial data output is disabled for uart1. sot1 serial data output pin for uart1 this applies when serial data output is enabled for uart1. 58 60 p92 d (cmos/h) general purpose i/o port this applies when the uart1 clock output is disabled. sck1 clock i/o pin for uart1 this applies when the uart1 clock output is enabled. as the input operates continuously when uart1 is set to input operation, output to the pin from other functions must be stopped unless done intentionally. 59 61 p93 d (cmos/h) general purpose i/o port this applies in all cases. sin2 serial data input pin for uart2 as the input operates continuously when uart2 is set to input operation, output to the pin from other functions must be stopped unless done intentionally. 60 62 p94 d (cmos/h) general purpose i/o port this applies when serial data output is disabled for uart2. sot2 serial data output pin for uart2 this applies when serial data output is enabled for uart2. 61 63 p95 d (cmos/h) general purpose i/o port this applies when the uart2 clock output is disabled. sck2 clock i/o pin for uart2 this applies when the uart2 clock output is enabled. as the input operates continuously when uart2 is set to input operation, output to the pin from other functions must be stopped unless done intentionally. 62 64 cs0 j (cmos) chip select pin for program rom 63 to 69 65 to 71 pa1 to pa7 i (cmos) general purpose i/o ports this applies for pins with chip select output disabled by the chip select control register. cs1 to cs7 output pins for the chip select function this applies for pins with chip select output enabled by the chip select control register. 70 72 p50 i (cmos) general purpose i/o port this applies when clk output is enabled. clk clk output pin
10 mb90610a series (continued) *1: fpt-100p-m05 *2: fpt-100p-m06 pin no. pin name circuit type function lqfp* 1 qfp* 2 71 73 p51 l (ttl) general purpose i/o port this applies when the external ready function is disabled. rdy ready input pin this applies when the external ready function is enabled. 72 74 p52 i (cmos) general purpose i/o port this applies when the hold function is disabled. hak hold acknowledge output pin this applies when the hold function is enabled. 73 75 p53 l (ttl) general purpose i/o port this applies when the hold function is disabled. hrq hold request input pin this applies when the hold function is enabled. 74 76 p54 i (cmos) general purpose i/o port this applies in 8-bit external bus mode or when output is disabled for the wr pin. wrh write strobe output pin for the upper 8 bits of the data bus this applies in 16-bit external bus mode and when output is enabled for the wr pin. 75 77 rst g (cmos/h) external reset request input pin 76 78 p55 i (cmos) general purpose i/o port this applies when output is disabled for the wr pin. wrl write strobe output pin for the lower 8 bits of the data bus this applies when output is enabled for the wr pin. 77 79 rd j (cmos) read strobe output pin for the data bus 78 80 ale j (cmos) ale (address latch enabling) output pin 21, 82 23, 84 v cc power supply power supply for the digital circuits 9, 40, 79 11, 42, 81 v ss power supply ground level for the digital circuits
mb90610a series 11 n i/o circuit type note: for pins with pull-up resistors, the resistance is disconnected when the pin outputs the l level or when in the standby state. (continued) type circuit remarks a ? max. 3 to 32 mhz ? oscillator feedback resistance: approximately 1 m w b ? cmos level i/o with standby control c ? n-channel open drain output ? cmos level hysteresis input with ad control d ? cmos level output ? cmos level hysteresis input with standby control x1 x0 standby control clock input standby control digital input digital output digital output r a/d disable digital input digital output a/d input r standby control digital input digital output digital output r
12 mb90610a series note: for pins with pull-up resistors, the resistance is disconnected when the pin outputs the l level or when in the standby state. (continued) type circuit remarks e ? cmos level input no standby control f ? cmos level hysteresis input no standby control g ? cmos level hysteresis input no standby control ? with pull-up h ? cmos level output ? cmos level hysteresis input no standby control i ? cmos level i/o ? pull-up resistor approximately 50 k w ? pin goes to high impedance during stop mode. digital input r digital input r digital input r digital output digital output digital input r standby control digital input digital output digital output r standby control
mb90610a series 13 (continued) note: for pins with pull-up resistors, the resistance is disconnected when the pin outputs the l level or when in the standby state. type circuit remarks j ? cmos level output ? pull-up resistor approximately 50 k w ? pin goes to high impedance during stop mode. k ? cmos level output ? ttl level input with standby control l ? cmos level output ? ttl level input ? pull-up resistor approximately 50 k w ? pin goes to high impedance during stop mode. m ? cmos level input no standby control digital output digital output standby control standby control digital input digital output digital output r standby control digital input digital output digital output r standby control digital input r
14 mb90610a series n handling devices 1. preventing latchup latchup occurs in a cmos ic if a voltage greater than v cc or less than v ss is applied to an input or output pin or if the voltage applied between v cc and v ss exceeds the rating. if latchup occurs, the power supply current increases rapidly resulting in thermal damage to circuit elements. therefore, ensure that maximum ratings are not exceeded in circuit operation. for the same reason, also ensure that the analog supply voltage does not exceed the digital supply voltage. 2. treatment of unused pins leaving unused input pins unconnected can cause misoperation. always pull-up or pull-down unused pins. 3. external reset input to reliably reset the controller by inputting an l level to the rst pin, ensure that the l level is applied for at least five machine cycles. take particular note when using an external clock input. 4. v cc and v ss pins ensure that all v cc pins are at the same voltage. the same applies for the v ss pins. 5. cautions when using an external clock drive the x0 pin only when using an external clock. 6. a/d converter power supply and the turn-on sequence for analog inputs always cut the a/d converter power supply (av cc , avrh, avrl) and analog inputs (an0 to an7) before disconnecting the digital power supply (v cc ). when turning the power on or off, ensure that avrh does not exceed av cc . also, when using the analog input pins as input ports, ensure that the input voltage does not exceed av cc . x0 x1 mb90610a series open ? using an external clock
mb90610a series 15 n block diagram clock control circuit ram interrupt controller 8 8 8 8 6 8 77 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p50 to p55 p60 to p67 p70 to p76 p80 to p86 i/o ports cpu f 2 mc-16l family core external interrupts 6 p90 to p95 8 8 irt0 to irt7 7 pa1 to pa7 x0, 1 rst hst md0 to md2 reload timer chip select outputs cs0 to cs7 tit0, tit1 tot0, tot1 8/16-bit ppg uart a/d converter (8/10-bit) external bus interface avcc avrh, avrl avss atg an0 to an7 sin0 to sin2 sot0 to sot2 sck0 to sck2 communication prescaler ppg0 ppg1 a00 to a23 d00 to d15 ale rd wrl, wrh hrq hak rdy clk f 2 mc-16 bus (output switching) 1channel 7 3 3 3 16 2 2 2 2 8 24
16 mb90610a series n f 2 mc-16l cpu programming model ah al dpr pcb dtb usb ssb adb 8 bits 16 bits 32 bits accumulator usp ssp ps pc user stack pointer system stack pointer processor status program counter direct page register program bank register data bank register user stack bank register system stack bank register additional data bank register 32 banks (max.) r7 r6 r5 r4 r3 r2 r1 r0 rw3 rw2 rw1 rw0 16 bits 000180 h + rp 10 h ? rw7 rw6 rw5 rw4 rl3 rl2 rl1 rl0 ilm rp ? istnzvc ccr ? dedicated registers ? processor states (ps) ? general-purpose registers
mb90610a series 17 n memory map ffffff h 000380 h 002000 h address 3# 000180 h 000100 h 0000c0 h 000000 h external rom/external bus ram registers peripherals : internal : external : no access type address #3 mb90611a 000500 h mb90613a 000d00 h
18 mb90610a series n i/o map (continued) address register name access resource name initial value 000000 h free *3 000001 h port 1 data register pdr1 r/w* por t 1 *8 xxxxxxxx 000002 h port 2 data register pdr2 r/w* por t 2 *7 xxxxxxxx 000003 h port 3 data register pdr3 r/w* por t 3 *7 xxxxxxxx 000004 h port 4 data register pdr4 r/w port 4 x x x x x x x x 000005 h port 5 data register pdr5 r/w port 5 C C x x x x x x 000006 h port 6 data register pdr6 r/w port 6 1 1 1 1 1 1 1 1 000007 h port 7 data register pdr7 r/w port 7 C x x x x x x x 000008 h port 8 data register pdr8 r/w port 8 C x x x x x x x 000009 h port 9 data register pdr9 r/w port 9 C C x x x x x x 00000a h port a data register pdra r/w port a x x x x x x x C 00000b h to 10 h vacancy *3 000011 h port 1 direction register ddr1 r/w* por t 1 *8 00000000 000012 h port 2 direction register ddr2 r/w* por t 2 *7 00000000 000013 h port 3 direction register ddr3 r/w* por t 3 *7 00000000 000014 h port 4 direction register ddr4 r/w port 4 0 0 0 0 0 0 0 0 000015 h port 5 direction register ddr5 r/w port 5 C C 0 0 0 0 0 0 000016 h analog input enable register ader r/w port 6 1 1 1 1 1 1 1 1 000017 h port 7 direction register ddr7 r/w port 7 C 0 0 0 0 0 0 0 000018 h port 8 direction register ddr8 r/w port 8 C 0 0 0 0 0 0 0 000019 h port 9 direction register ddr9 r/w port 9 C C 0 0 0 0 0 0 00001a h port a direction register ddra r/w port a 0 0 0 0 0 0 0 C 00001b h to 1f h vacancy *3 000020 h serial mode register 0 smr0 r/w! uart0 (sci) 00000000 000021 h serial control register 0 scr0 r/w! 0 0 0 0 0 1 0 0 000022 h serial input data register 0/ serial output data register 0 sidr0/ sodr0 r/w xxxxxxxx 000023 h serial status register 0 ssr0 r/w! 0 0 0 0 1 C 0 0 000024 h serial mode register 1 smr1 r/w! uart1 (sci) 00000000 000025 h serial control register 1 scr1 r/w! 0 0 0 0 0 1 0 0 000026 h serial input data register 1/ serial output data register 1 sidr1/ sodr1 r/w xxxxxxxx 000027 h serial status register 1 ssr1 r/w! 0 0 0 0 1 C 0 0
mb90610a series 19 (continued) address register name access resource name initial value 000028 h interrupt/dtp enable register enir r/w dtp/external interrupt 00000000 000029 h interrupt/dtp request register eirr r/w 0 0 0 0 0 0 0 0 00002a h interrupt level setting register elvr r/w 00000000 00002b h 00000000 00002c h ad control status register adcs r/w! a/d converter 00000000 00002d h 00000000 00002e h ad data register adcr r/w! *4 xxxxxxxx 00002f h 000000xx 000030 h ppg0 operation mode control register ppgc0 r/w ppg0 000000C1 000031 h ppg1 operation mode control register ppgc1 r/w ppg1 000000C1 000032 h , 33 h vacancy *3 000034 h ppg0 reload register prl0 r/w ppg0 xxxxxxxx 000035 h xxxxxxxx 000036 h ppg1 reload register prl1 r/w ppg1 xxxxxxxx 000037 h xxxxxxxx 000038 h control status register tmcsr0 r/w! 16-bit reload timer 0 00000000 000039 h CCCC0000 00003a h 16-bit timer register/ 16-bit reload register tmr0/ tmrlr0 r/w xxxxxxxx 00003b h xxxxxxxx 00003c h control status register tmcsr1 r/w! 16-bit reload timer 1 00000000 00003d h CCCC0000 00003e h 16-bit timer register/ 16-bit reload register tmr1/ tmrlr1 r/w xxxxxxxx 00003f h xxxxxxxx 000040 h to 43 h vacancy *3 000044 h serial mode register 2 smr2 r/w! uart2 (sci) 00000000 000045 h serial control register 2 scr2 r/w! 0 0 0 0 0 1 0 0 000046 h serial input data register 2/ serial output data register 2 sidr2/ sodr2 r/w xxxxxxxx 000047 h serial status register 2 ssr2 r/w! 0 0 0 0 1 C 0 0 000048 h cs control register 0 cscr0 r/w chip select function CCCC0000 000049 h cs control register 1 cscr1 r/w CCCC0000 00004a h cs control register 2 cscr2 r/w CCCC0000 00004b h cs control register 3 cscr3 r/w CCCC0000
20 mb90610a series (continued) address register name access *2 resource name initial value 00004c h cs control register 4 cscr4 r/w chip select function CCCC0000 00004d h cs control register 5 cscr5 r/w CCCC0000 00004e h cs control register 6 cscr6 r/w CCCC0000 00004f h cs control register 7 cscr7 r/w CCCC0000 000050 h vacancy *3 000051 h uart0 (sci) machine clock division control register cdcr0 w uart0 (sci) CCCC1111 000052 h vacancy *3 000053 h uart1 (sci) machine clock division control register cdcr1 w uart1 (sci) CCCC1111 000054 h vacancy *3 000055 h uart2 (sci) machine clock division control register cdcr2 w uart2 (sci) CCCC1111 000056 h to 8f h vacancy *3 000090 h to 9e h reserved system area *1 00009f h delayed interrupt generate/ release register dirr r/w delayed interrupt generation module CCCCCCC0 0000a0 h low power consumption mode control register lpmcr r/w! low power consumption 00011000 0000a1 h clock selection register ckscr r/w! low power consumption 11111100 0000a2 h to a4 h vacancy *3 0000a5 h auto-ready function selection register arsr w external pins 0 0 1 1 C C 0 0 0000a6 h external address output control register hacr w external pins 0 0 0 0 0 0 0 0 0000a7 h bus control signal selection register ecsr w external pins C 0 0 0 * 0 0 0 0000a8 h watchdog timer control register wdtc r/w! watchdog timer x x x x x 1 1 1 0000a9 h timebase timer control register tbtc r/w! timebase timer 1 C C 0 0 1 0 0 0000aa h to af h vacancy *3 0000b0 h interrupt control register 00 icr00 r/w! interrupt controller 00000111 0000b1 h interrupt control register 01 icr01 r/w! 0 0 0 0 0 1 1 1 0000b2 h interrupt control register 02 icr02 r/w! 0 0 0 0 0 1 1 1 0000b3 h interrupt control register 03 icr03 r/w! 0 0 0 0 0 1 1 1 0000b4 h interrupt control register 04 icr04 r/w! 0 0 0 0 0 1 1 1 0000b5 h interrupt control register 05 icr05 r/w! 0 0 0 0 0 1 1 1
mb90610a series 21 (continued) initial values 0 : the initial value for this bit is 0. 1 : the initial value for this bit is 1. * : the initial value for this bit is 1 or 0. (determined by the level of the md0 to md2 pins.) x : the initial value for this bit is undefined. C : this bit is not used. the initial value is undefined. *1: access prohibited. *2: this is the only external access area in the area below address 0000ff h . access this address as an external i/o area. *3: areas marked as free in the i/o map are reserved areas. these areas are accessed by internal access. no access signals are output on the external bus. *4: only bit 15 can be written. the other bits are written to by the test function. reading bits 10 to 15 returns zeros. *5: the r/w! symbol in the read/write column indicates that some bits are read-only or write-only. see the resources register list for details. *6: using a read-modify-write instruction (such as the bit set instruction) to access one of the registers indicated by r/w!, r/w*, or w in the read/write column sets the specified bit to the desired value. however, this can cause misoperation if the other register bits include write-only bits. therefore, do not use read-modify-write instructions to access these registers. *7: this register is only available when the address/data bus is in multiplex mode. access to the register is prohibited in non-multiplex mode. *8: this register is only available when the external data bus is in 8-bit mode. access to the register is prohibited in 16-bit mode. note: the initial values listed for write-only bits are the initial values set by a reset. they are not the values returned by a read. also, lpmcr/ckscr/wdtc are sometimes initialized and sometimes not initialized, depending on the reset type. the listed initial values are for when these registers are initialized. address register name access resource name initial value 0000b6 h interrupt control register 06 icr06 r/w! interrupt controller 00000111 0000b7 h interrupt control register 07 icr07 r/w! 0 0 0 0 0 1 1 1 0000b8 h interrupt control register 08 icr08 r/w! 0 0 0 0 0 1 1 1 0000b9 h interrupt control register 09 icr09 r/w! 0 0 0 0 0 1 1 1 0000ba h interrupt control register 10 icr10 r/w! 0 0 0 0 0 1 1 1 0000bb h interrupt control register 11 icr11 r/w! 0 0 0 0 0 1 1 1 0000bc h interrupt control register 12 icr12 r/w! 0 0 0 0 0 1 1 1 0000bd h interrupt control register 13 icr13 r/w! 0 0 0 0 0 1 1 1 0000be h interrupt control register 14 icr14 r/w! 0 0 0 0 0 1 1 1 0000bf h interrupt control register 15 icr15 r/w! 0 0 0 0 0 1 1 1 0000c0 h to ff h external area *2
22 mb90610a series n interrupt vector and interrupt control register assignments to interrupt sources : indicates that the interrupt request flag is cleared by the i 2 os interrupt clear signal (no stop request). : indicates that the interrupt request flag is cleared by the i 2 os interrupt clear signal (with stop request). : indicates that the interrupt request flag is not cleared by the i 2 os interrupt clear signal. note: do not specify i 2 os activation in interrupt control registers that do not support i 2 os. interrupt source i 2 os sup- port interrupt vector interrupt control register number address icr address reset #08 08 h ffffdc h int 9 instruction #09 09 h ffffd8 h exception #10 0a h ffffd4 h external interrupt #0 #11 0b h ffffd0 h icr00 0000b0 h external interrupt #1 #13 0d h ffffc8 h icr01 0000b1 h external interrupt #2 #15 0f h ffffc0 h icr02 0000b2 h external interrupt #3 #17 11 h ffffb8 h icr03 0000b3 h external interrupt #4 #19 13 h ffffb0 h icr04 0000b4 h external interrupt #5 #21 15 h ffffa8 h icr05 0000b5 h external interrupt #6 #23 17 h ffffa0 h icr06 0000b6 h uart0 ? transmit complete #24 18 h ffff9c h external interrupt #7 #25 19 h ffff98 h icr07 0000b7 h uart1 ? transmit complete #26 1a h ffff94 h ppg #0 #27 1b h ffff90 h icr08 0000b8 h ppg #1 #28 1c h ffff8c h 16-bit reload timer #0 #29 1d h ffff88 h icr09 0000b9 h 16-bit reload timer #1 #30 1e h ffff84 h a/dc measurement complete #31 1f h ffff80 h icr10 0000ba h uart2 ? transmit complete #33 21 h ffff78 h icr11 0000bb h timebase timer interval interrupt #34 22 h ffff74 h uart2 ? receive complete #35 23 h ffff70 h icr12 0000bc h uart1 ? receive complete #37 25 h ffff68 h icr13 0000bd h uart0 ? receive complete #39 27 h ffff60 h icr14 0000be h delayed interrupt generation module #42 2a h ffff54 h icr15 0000bf h
mb90610a series 23 n peripheral resources 1. parallel port the mb90610a series has 58 i/o pins, 18 output pins, and 8 open drain output pins. ports 1 to 5 and ports 7 to a are i/o ports. the ports are inputs when the corresponding direction register bit is 0 and outputs when the corresponding bit is 1. port 1 is only available when the external data bus is in 8-bit mode. access is prohibited in 16-bit mode. ports 2 and 3 are only available when the address/data bus is in multiplex mode. access is prohibited in non- multiplex mode. port 6 is an open drain port. port 6 pins can only be used as ports when the analog input enable register is 0. (1) register configuration notes: no register bits are provided for bit 6 to 7 of port 5. no register bit is provided for bit 7 of port 7. no register bit is provided for bit 7 of port 8. no register bits are provided for bits 6 to 7 of port 9. no register bit is provided for bit 0 of port a. bit read/write initial value bit pd 7pd 6pd 5pd 4pd 3pd 2pd 1pd 0 pdr (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) 15 14 13 12 11 10 9 8 pd 7pd 6pd 5pd 4pd 3pd 2pd 1pd 0 pdr (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) 76543210 read/write initial value port data register address : pdr1 000001 h : pdr3 000003 h : pdr5 000005 h : pdr7 000007 h : pdr9 000009 h port data register address : pdr2 000002 h : pdr4 000004 h : pdr6 000006 h : pdr8 000008 h : pdra 00000a h bit read/write initial value bit dd 7dd 6dd 5dd 4dd 3dd 2dd 1dd 0 ddr (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 15 14 13 12 11 10 9 8 dd 7dd 6dd 5dd 4dd 3dd 2dd 1dd 0 ddr (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 76543210 read/write initial value port direction register address : ddr1 000011 h : ddr3 000013 h : ddr5 000015 h : ddr7 000017 h : ddr9 000019 h port direction register address : ddr2 000012 h : ddr4 000014 h : ddr8 000018 h : ddra 00001a h
24 mb90610a series note: no register bits are provided for bit 6 to 7 of port 5. no register bit is provided for bit 7 of port 7. no register bit is provided for bit 7 of port 8. no register bits are provided for bits 6 to 7 of port 9. no register bit is provided for bit 0 of port a. port 6 does not have a ddr. (2) register details ? port data registers note: no register bits are provided for bit 6 to 7 of port 5. no register bit is provided for bit 7 of port 7. no register bit is provided for bit 7 of port 8. no register bits are provided for bits 6 to 7 of port 9. no register bit is provided for bit 0 of port a. port 1 is only available when the external data bus is in 8-bit mode. access is prohibited in 16-bit mode. ports 2, 3 are only available in multiplex mode. access is prohibited in non-multiplex mode. bit read/write initial value ade7 ade6 ade5 ade4 ade3 ade2 ade1 ade0 ader (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) 15 14 13 12 11 10 9 8 analog input enable register ader 000016 h bit read/write initial value bit pd 7pd 6pd 5pd 4pd 3pd 2pd 1pd 0 pdr (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) 15 14 13 12 11 10 9 8 pd 7pd 6pd 5pd 4pd 3pd 2pd 1pd 0 pdr (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) 76543210 read/write initial value port data register address : pdr1 000001 h : pdr3 000003 h : pdr5 000005 h : pdr7 000007 h : pdr9 000009 h port data register address : pdr2 000002 h : pdr4 000004 h : pdr6 000006 h : pdr8 000008 h : pdra 00000a h
mb90610a series 25 ? port direction registers when pins are used as ports, the register bits control the corresponding pins as follows. 0: input mode 1: output mode bits are set to 0 by a reset. note: no register bits are provided for bit 6 to 7 of port 5. no register bit is provided for bit 7 of port 7. no register bit is provided for bit 7 of port 8. no register bit is provided for bit 0 of port a. no register bits are provided for bits 6 to 7 of port 9. port 6 does not have a ddr. port 1 is only available when the external data bus is in 8-bit mode. access is prohibited in 16-bit mode. ports 2 and 3 are only available in multiplex mode. access is prohibited in non-multiplex mode. ? analog input enable register controls each pin of port 6 as follows. 0: port input mode 1: analog input mode bits are set to 1 by a reset. note: inputting an intermediate level signal in port input mode causes an input leak current to flow. therefore, set to analog input mode when applying an analog input. bit read/write initial value bit dd 7dd 6dd 5dd 4dd 3dd 2dd 1dd 0 ddr (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 15 14 13 12 11 10 9 8 dd 7dd 6dd 5dd 4dd 3dd 2dd 1dd 0 ddr (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 76543210 read/write initial value port direction register address : ddr1 000011 h : ddr3 000013 h : ddr5 000015 h : ddr7 000017 h : ddr9 000019 h port direction register address : ddr2 000012 h : ddr4 000014 h : ddr8 000018 h : ddra 00001a h bit read/write initial value ade7 ade6 ade5 ade4 ade3 ade2 ade1 ade0 ader (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) 15 14 13 12 11 10 9 8 analog input enable register ader 000016 h
26 mb90610a series (3) block diagrams internal data bus data register direction register data register read data register write direction register write direction register read pin internal data bus data register ader data register read data register write ader register write ader register read pin rmw (read-modify-write instruction) ? i/o port ? open drain port (also used as analog inputs)
mb90610a series 27 (4) port pin allocation ports 1, 2, 3, 4, and 5 on the mb90610a series share pins with the external bus. the pin functions are determined by the bus mode and register settings. note: the upper address, wrl , wrh , hak , hrq, rdy, and clk can be set for use as ports by function selection. pin function non-multiplex mode multiplex mode external address control external address control enable (address) disable (port) enable (address) disable (port) external bus width external bus width external bus width external bus width 8-bit 16-bit 8-bit 16-bit 8-bit 16-bit 8-bit 16-bit d07 to d00 ad07 to ad00 d07 to d00 ad07 to ad00 p17 to p10/ d15 to d08/ ad15 to ad08 port d15 to d08 port d15 to d08 a15 to a08 ad15 to ad08 a15 to a08 ad15 to ad08 p27 to p20/ a07 to a00 a07 to a00 a07 to a00 port p37 to p30/ a15 to a08 a15 to a08 a15 to a08 p47 to p40/ a23 to a16 a23 to a16 port a23 to a16 port p57/ale ale ale rd rd rd p55/wrl wrl wrl p54/wrh port wrh port wrh port wrh port wrh p53/hrq hrq hrq p52/hak hak hak p51/rdy rdy rdy p50/clk clk clk
28 mb90610a series 2. uart 0/1/2 (sci) uart 0/1/2 are serial i/o ports that can be used for clk asynchronous (start-stop synchronization) or clk synchronous (i/o expansion serial) data transfer. the ports have the following features. ? full duplex, double buffered ? supports clk asynchronous (start-stop synchronization) and clk synchronous (i/o expansion serial) data transfer ? multi-processor mode support ? built-in dedicated baud rate generator clk asynchronous: 62500/31250/19230/9615/4808/2404/1202 bps clk synchronous: 2 m/1 m/500 k/250 k bps ? supports flexible baud rate setting using an external clock ? error detect function (parity, framing, and overrun) ? nrz type transmission signal ? intelligent i/o service support (1) register configuration bit read/write initial value bit pen p sbl cl a/d rec rxe txe scr (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (1) (r/w) (0) (r/w) (0) 15 14 13 12 11 10 9 8 md1 md0 cs2 cs1 cs0 scke soe smr (r/w) (0) (r/w) (0) (w) (0) (w) (0) (w) (0) (? (? (r/w) (0) (r/w) (0) 76543210 read/write initial value serial control register address : channel 0 000021 h : channel 1 000025 h : channel 2 000045 h serial mode register address : channel 0 000020 h : channel 1 000024 h : channel 2 000044 h bit read/write initial value bit pe ore fre rdrf tdre rie tie ssr (r) (0) (r) (0) (r) (0) (r) (0) (r) (1) (? (? (r/w) (0) (r/w) (0) 15 14 13 12 11 10 9 8 d7 d6 d5 d4 d3 d2 d1 d0 sidr (read) sodr (write) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) 76543210 read/write initial value serial status register address : channel 0 000023 h : channel 1 000027 h : channel 2 000047 h bit read/write initial value div3 div1 div1 div0 cdcr (? (? (? (? (? (? (? (? (w) (1) (w) (1) (w) (1) (w) (1) 15 14 13 12 11 10 9 8 machine clock division control register address : channel 0 000051 h : channel 1 000053 h : channel 2 000055 h input data register/ output data register address : channel 0 000022 h : channel 1 000026 h : channel 2 000046 h
mb90610a series 29 (2) block diagram control signals dedicated baud rate generator 16-bit timer 0 (internal connection) external clock sin clock select circuit receive interrupt (to cpu) transmit interrupt (to cpu) receive control circuit start bit detect circuit receive bit counter receive parity counter transmit control circuit transmit start circuit transmit bit counter transmit parity counter receive status evaluation circuit receive shifter receive complete transmit shifter transmit start receive error indication signal for ei 2 os (to cpu) sidr sodr f 2 mc-16 bus smr register md1 md0 cs2 cs1 cs0 scke soe scr register ssr register control signals transmit clock receive clock sot pen p sbl cl a/d rec rxe txe pe ore fre rdrf tdre rie tie sck
30 mb90610a series 3. 10-bit 8-input a/d converter (with 8-bit resolution mode) the 10-bit 8-input a/d converter converts analog input voltages to digital values. the a/d converter has the following features. ? conversion time: minimum of 6.13 m s per channel (98 machine cycles/16 mhz machine clock. this includes the sample and hold time) ? sample and hold time: minimum of 3.75 m s per channel (60 machine cycles/16 mhz machine clock) ? uses rc-type successive approximation conversion with a sample and hold circuit. ? 10-bit or 8-bit resolution ? eight program-selectable analog input channels single conversion mode : selectively convert a one channel. scan conversion mode : continuously convert multiple channels. maximum of 8 program-selectable channels. continuous conversion mode : repeatedly convert specified channels. stop conversion mode : convert one channel then halt until the next activation. (enables synchronization of the conversion start timing.) ? an a/d conversion completion interrupt request to the cpu can be generated on the completion of a/d conversion. this interrupt can activate i 2 os to transfer the result of a/d conversion to memory and is suitable for continuous operation. ? activation by software, external trigger (falling edge), or timer (rising edge) can be selected. (1) register configuration bit read/write initial value busy int inte paus sts1 sts0 strt reserved adcs1 (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (w) (0) (? (0) 15 14 13 12 11 10 9 8 a/d control status register (upper) address : 00002d h bit read/write initial value md1 md0 ans2 ans1 ans0 ane2 ane1 ane0 adcs0 (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 76543210 a/d control status register (lower) address : 00002c h bit read/write initial value s10d9d8 adcr1 (r/w) (0) (r) (0) (r) (0) (r) (0) (r) (0) (r) (0) (r) (x) (r) (x) 15 14 13 12 11 10 9 8 a/d data register (upper) address : 00002e h bit read/write initial value d7 d6 d5 d4 d3 d2 d1 d0 adcr0 (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) 76543210 a/d data register (lower) address : 00002f h
mb90610a series 31 (2) block diagram av cc avrh avrl an0 an1 an2 an3 an4 an5 an6 an7 mpx sample and hold circuit comparator d/a converter successive approximation register data register a/d control register 1 a/d control register 2 adcr adcs atg timer (reload timer 1 output) f timer activation trigger activation operating clock prescaler av ss input circuit decoder data bus
32 mb90610a series 4. 8/16-bit ppg this block contains the 8-bit reload timer module. the block performs ppg output in which the pulse output is controlled by the operation of the timer. the hardware consists of two 8-bit down-counters, four 8-bit reload registers, one 16-bit control register, two external pulse output pins, and two interrupt outputs. the ppg has the following functions. ? 8-bit ppg output in 2-channel independent operation mode: two independent ppg output channels are available. ? 16-bit ppg output operation mode : one 16-bit ppg output channel is available. ? 8+8-bit ppg output operation mode : variable-period 8-bit ppg output operation is available by using the output of channel 0 as the clock input to channel 1. ? ppg output operation: outputs pulse waveforms with variable period and duty ratio. can be used as a d/a converter in conjunction with an external circuit. (1) register configuration bit read/write initial value bit pen1 pcs1 poe1 pie1 puf1 md1 md0 reserved ppgc1 (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (? (1) 15 14 13 12 11 10 9 8 pen0 poe0 pie0 puf0 pcm1 pcm0 reserved ppgc0 (r/w) (0) (? (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (? (1) 76543210 read/write initial value ppg1 operation mode control register address : channel 1 000031 h bit read/write initial value prlh0, 1 (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) 15 14 13 12 11 10 9 8 reload register h address : channel 0 000035 h : channel 1 000037 h bit read/write initial value prll0, 1 (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) 76543210 reload register l address : channel 0 000034 h : channel 1 000036 h ppg0 operation mode control register address : channel 0 000030 h
mb90610a series 33 (2) block diagram ppg0 output latch pcnt (down-counter) s r q output enable l/h selector prlbh0 ppgc0 peripheral clock divided by 16 peripheral clock divided by 4 peripheral clock prll0 prlh0 l-side data bus h-side data bus ppg0 clear invert pen0 reload ch.1 borrow irq count clock selection timebase counter output main clock divided by 512 l/h select pie 0 puf0 (operation mode control) ? 8/16-bit ppg (channel 0)
34 mb90610a series ppg1 output latch pcnt (down-counter) s r q output enable l/h selector prlbh1 ppgc1 peripheral clock prll1 prlh1 l-side data bus h-side data bus ppg1 clear invert pen1 reload channel 0 borrow irq timebase counter output main clock divided by 512 l/h select pie1 puf1 (operation mode control) count clock selection ? 8/16-bit ppg (channel 1)
mb90610a series 35 5. 16-bit reload timer (with event count function) the 16-bit reload timers consists of a 16-bit down-counter, a 16-bit reload register, one input (tin) and one output (tot) pin, and a control register. the input clock can be selected from one external clock and three types of internal clock. the output pin (tot) outputs a toggle waveform in reload mode and a rectangular waveform during counting in one-shot mode. the input pin (tin) functions as the event input in event count mode and as the trigger input or gate input in internal clock mode. this product has two internal 16-bit reload timer channels. (1) register configuration timer control status register (upper) address : channel 0 000039 h : channel 1 00003d h bit read/write initial value bit csl1 csl2 mod2 mod1 (? (? (? (? (? (? (? (? (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 15 14 13 12 11 10 9 8 mod0 oute outl reld inte uf cnte trg tmcsr (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 76543210 read/write initial value timer control status register (lower) address : channel 0 000038 h : channel 1 00003c h 16-bit timer register (upper)/ 16-bit reload register (upper) address : channel 0 00003b h : channel 1 00003f h bit read/write initial value bit (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) 15 14 13 12 11 10 9 8 tmr/ tmrlr (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) 76543210 read/write initial value 16-bit timer register (lower)/ 16-bit reload register (lower) address : channel 0 00003a h : channel 1 00003e h
36 mb90610a series (2) block diagram 16-bit reload register 16-bit down-counter uf clock selector reload out ctl csl1 csl0 mod2 mod1 mod0 16 8 16 2 3 2 in ctl f 2 f 2 f 2 135 3 peripheral clock prescaler clear exck gate re-trigger irq port (tin) port (tout) output enable serial baud rate a/dc reld oute outl inte uf cnte trg clear i 2 osclr f 2 mc-16 bus
mb90610a series 37 6. chip select function this module generates chip select signals to simplify connection of memory or i/o devices. the module has 8 chip select output pins. the hardware outputs the chip select signals from the pins when it detects access of an address in the areas specified in the pin registers. (1) register configuration (2) block diagram bit bit actl opel csa1 csa0 chip select control register (odd numbers: cscr1/3/5/7) 15 14 13 12 11 10 9 8 actl opel csa1 csa0 chip select control register (even numbers: cscr0/2/4/6) 76543210 address : 000049 h : 00004b h : 00004d h : 00004f h address : 000048 h : 00004a h : 00004c h : 00004e h selector selector chip select control register 0 chip select control register 1 cs0 (for the program rom area) cs1 cs6 address (from cpu) address decoder address decoder a23 a16 a15 a08 a07 a00 decode signal program area decode selection setting selection setting selector selector chip select control register 6 chip select control register 7 cs7 selection setting selection setting
38 mb90610a series 7. dtp/external interrupts the dtp (data transfer peripheral) is a peripheral block that interfaces external peripherals to the f 2 mc-16l cpu. the dtp receives dma and interrupt processing requests from external peripherals and passes the requests to the f 2 mc-16l cpu to activate the extended intelligent i/o service or interrupt processing. two request levels (h and l) are provided for extended intelligent i/o service. for external interrupt requests, generation of interrupts on a rising or falling edge as well as on h, l levels can be selected, giving a total of four types. (1) register configuration (2) block diagram bit read/write initial value en7 en6 en5 en4 en3 en2 en1 en0 enir (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 76543210 interrupt/dtp enable register address : 000028 h bit read/write initial value er7 er6 er5 er4 er3 er2 er1 er0 eirr (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 15 14 13 12 11 10 9 8 interrupt/dtp register address : 000029 h bit read/write initial value lb7 la7 lb6 la6 lb5 la5 lb4 la4 (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 15 14 13 12 11 10 9 8 request level setting register (upper) address : 00002b h bit read/write initial value lb3 la3 lb2 la2 lb1 la1 lb0 la0 elvr (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 76543210 request level setting register (lower) address : 00002a h 8 8 8 8 8 interrupt/dtp enable register interrupt/dtp register request level setting register gate request f/f edge detect circuit request input interrupt input f 2 mc-16 bus
mb90610a series 39 8. delayed interrupt generation module the delayed interrupt generation module is used to generate the task switching interrupt. interrupt requests to the f 2 mc-16l cpu can be generated and cleared by software using this module. (1) register configuration (2) block diagram bit read/write initial value r0 dirr (? (? (? (? (? (? (? (? (? (? (? (? (? (? (r/w) (0) 15 14 13 12 11 10 9 8 address : 00009f h delayed interrupt generate/ clear decoder delayed interrupt generate/clear decoder interrupt latch f 2 mc-16 bus
40 mb90610a series 9. watchdog timer and timebase timer functions the watchdog timer consists of a 2-bit watchdog counter, a control register, and a watchdog reset controller. the watchdog counter uses the carry-up signal from the 18-bit timebase timer as its clock source. in addition to the 18-bit timer, the timebase timer contains an interval interrupt control circuit. the timebase timer uses the main clock, regardless of the value of the mcs bit in the ckscr register. (1) register configuration (2) block diagram bit read/write initial value ponr stbr wrst erst srst wte wt1 wt0 wdtc (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (w) (1) (w) (1) (w) (1) 76543210 watchdog timer control register address : 0000a8 h bit read/write initial value reserved tbie tbof tbr tbc1 tbc0 tbtc (? (1) (? (? (? (? (r/w) (0) (r/w) (0) (w) (1) (r/w) (0) (r/w) (0) 15 14 13 12 11 10 9 8 timebase timer control register address : 0000a9 h tbtc tbc1 tbc0 tbr tbie tbof ponr stbr wrst erst srst selector and q selector 2-bit counter clr clr watchdog reset activation circuit wt1 wdtc wt0 wte 2 12 2 12 timebase interrupt s r 2 14 2 16 2 19 tbtres timebase timer clock input 2 14 2 16 2 19 of main clock (osc oscillator) wdgrst to internal reset activation circuit from power-on detection from hardware standby control circuit rst pin from the rst bit of the stbyc register f 2 mc-16 bus
mb90610a series 41 10. low power control circuits (cpu intermittent operation function, oscillation stabilization delay time, and clock multiplier function) the following operation modes are available: pll clock mode, pll sleep mode, timer mode, main clock mode, main sleep mode, stop mode, and hardware standby mode. operation modes other than pll clock mode are classified as low power consumption modes. in main clock mode and main sleep mode, the device operates on the main clock only (osc oscillator clock). the pll clock (vco oscillator clock) is stopped in these modes and the main clock divided by 2 is used as the operating clock. in pll sleep mode and main sleep mode, the cpu's operating clock only is stopped and other elements continue to operate. in timer mode, only the timebase timer operates. stop mode and hardware standby mode stop the oscillator. these modes maintain existing data with minimum power consumption. the cpu intermittent operation function provides an intermittent clock to the cpu when register, internal memory, internal resource, or external bus access is performed. this function reduces power consumption by lowering the cpu execution speed while still providing a high-speed clock to internal resources. the pll clock multiplier ratio can be set to 1, 2, 3, 4 by the cs1, 0 bits. the ws1, 0 bits set the delay time to wait for the main clock oscillation to stabilize when recovering from stop mode or hardware standby mode. (1) register configuration bit read/write initial value stp slp spl rst reserved cg1 cg0 reserved lpmcr (w) (0) (w) (0) (r/w) (0) (w) (1) (? (1) (r/w) (0) (r/w) (0) (? (0) 76543210 low power consumption mode control register address : 0000a0 h bit read/write initial value reserved mcm ws1 ws0 reserved mcs cs1 cs0 ckscr (? (1) (r) (1) (r/w) (1) (r/w) (1) (? (1) (r/w) (1) (r/w) (0) (r/w) (0) 15 14 13 12 11 10 9 8 clock select register address : 0000a1 h
42 mb90610a series (2) block diagram main clock (osc oscillator) mcm mcs cs1 cs0 cg1 cg0 slp stp pll multiplier circuit 1234 1/2 cpu clock selector cycle selection circuit for the cpu intermittent operation function standby control circuit rst release hst activate ws1 ws0 oscillation stabilization delay time selector spl internal reset generation circuit rst pin high impedance control circuit cpu clock generator peripheral clock generator timebase timer 2 4 2 13 2 15 2 18 clock input 2 19 2 16 2 14 2 12 lpmcr lpmcr ckscr ckscr ckscr lpmcr lpmcr 0/9/17/33 intermittent cycle selection cpu clock peripheral clock hst pin interrupt request or rst timebase clock pin hi-z rst pin internal rst to watchdog timer wdgrst f 2 mc-16 bus
mb90610a series 43 main mcs = 1 mcm = 1 cs1/0 = xx main ? pllx mcs = 0 mcm = 1 cs1/0 = xx pll1 ? main mcs = 1 mcm = 0 cs1/0 = 00 pll2 ? main mcs = 1 mcm = 0 cs1/0 = 01 pll3 ? main mcs = 1 mcm = 0 cs1/0 = 10 pll4 ? main mcs = 1 mcm = 0 cs1/0 = 11 pll multiplier = 1 mcs = 0 mcm = 0 cs1/0 = 00 pll multiplier = 2 mcs = 0 mcm = 0 cs1/0 = 01 pll multiplier = 3 mcs = 0 mcm = 0 cs1/0 = 10 pll multiplier = 4 mcs = 0 mcm = 0 cs1/0 = 11 (1) (6) (7) (7) (7) (7) (2) (3) (4) (6) (6) (5) (6) (6) power-on (1) (2) (3) (4) (5) (6) (7) mcs bit cleared pll clock oscillation stabilization delay complete and cs1/0 = ?0 pll clock oscillation stabilization delay complete and cs1/0 = ?1 pll clock oscillation stabilization delay complete and cs1/0 = ?0 pll clock oscillation stabilization delay complete and cs1/0 = ?1 mcs bit set (including a hardware standby or watchdog reset) pll clock and main clock synchronized timing ? state transition diagram for clock selection
44 mb90610a series 11. interrupt controller the interrupt control registers are located in the interrupt controller. an interrupt control register is provided for each i/o with an interrupt function. the registers have the following three functions. ? set the interrupt level of the corresponding peripheral. ? select whether to treat interrupts from the corresponding peripheral as standard interrupts or activate the extended intelligent i/o service. ? select the extended intelligent i/o service channel. (1) register configuration note: do not access these registers using read-modify-write instructions as this can cause misoperation. read/write initial value (w) (0) (w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (1) (r/w) (1) (r/w) (1) bit 15 14 13 12 11 10 9 8 bit76543210 ics3 ics2 ics1 or s1 ics0 or s0 ise il2 il1 il0 icrxx ics3 ics2 ics1 or s1 ics0 or s0 ise il2 il1 il0 icrxx (w) (0) (w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (1) (r/w) (1) (r/w) (1) read/write initial value interrupt control register address : icr01 0000b1 h : icr03 0000b3 h : icr05 0000b5 h : icr07 0000b7 h : icr09 0000b9 h : icr11 0000bb h : icr13 0000bd h : icr15 0000bf h interrupt control register address : icr00 0000b0 h : icr02 0000b2 h : icr04 0000b4 h : icr06 0000b6 h : icr08 0000b8 h : icr10 0000ba h : icr12 0000bc h : icr14 0000be h
mb90610a series 45 (2) block diagram ise il2 il1 il0 determine priority of interrupt or i 2 os interrupt/ i 2 os request (peripheral resource) 4 4 32 s1 s0 detect i 2 os completion condition i 2 os completion condition 2 2 2 ics3 ics2 ics1 ics0 i 2 os vector selection i 2 os vector (cpu) 4 4 4 3 (cpu) interrupt level 4 i 2 os selection f 2 mc-16 bus
46 mb90610a series 12. external bus terminal control circuit this circuit controls the external bus terminals intended to extend outwardly the cpus address/data bus. (1) register configuration (2) block diagram bit read/write initial value ior1 ior0 hmr1 hmr0 lmr1 lmr0 arsr (w) (0) (w) (0) (w) (1) (w) (1) (? (? (? (? (w) (0) (w) (0) 15 14 13 12 11 10 9 8 register for selection of auto ready function address : 0000a5 h bit read/write initial value e23 e22 e21 e20 e19 e18 e17 e16 hacr (w) (0) (w) (0) (w) (0) (w) (0) (w) (0) (w) (0) (w) (0) (w) (0) 76543210 register for control of external address output address : 0000a6 h bit read/write initial value lmbs wre hmbs iobs hde rye cke ecsr (? (? (w) (0) (w) (0) (w) (1/0) (w) (0) (w) (0) (w) (0) (w) (0) 15 14 13 12 11 10 9 8 register for selection of bus control signal address : 0000a7 h p5 p4 p3 p2 p1 access control data control p1 data p1 direction access control access control rb p5 p1
mb90610a series 47 n electrical characteristics 1. absolute maximum rating (v ss = av ss = 0.0 v) *1: av cc , avrh, and avrl must not exceed v cc . similarly, it may not exceed avrl, nor avrh. *2: v i and v o must not exceed v cc + 0.3 v. *3: the maximum output current must not be exceeded at any individual pin. *4: the average output current is the rating for the current from an individual pin averaged over a duration of 100 ms. *5: the average total output current is the rating for the current from all pins averaged over a duration of 100 ms. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol rating unit remarks min. max. power supply voltage v cc v ss C 0.3 v ss + 7.0 v av cc * 1 v ss C 0.3 v ss + 7.0 v avrh* 1 avrl* 1 v ss C 0.3 v ss + 7.0 v input voltage* 2 v i v ss C 0.3 v cc + 0.3 v output voltage* 2 v o v ss C 0.3 v cc + 0.3 v l level maximum output current* 3 i ol 15 ma l level average output current* 4 i olav 4ma l level total maximum output current s i ol 100 ma l level total average output current* 5 s i olav 50 ma h level maximum output current* 3 i oh C15 ma h level average output current* 4 i ohav C4 ma h level total maximum output current s i oh C100 ma h level total average output current* 5 s i ohav C50 ma power consumption p d +400 mw operating temperature t a C40 +85 c storage temperature t stg C55 +150 c
48 mb90610a series 2. recommended operating conditions (v ss = 0.0 v) warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. parameter symbol rating unit remarks min. max. power supply voltage v cc 2.7 5.5 v for normal operation 2.0 5.5 v to maintain statuses in stop mode operating temperature t a C40 +85 c
mb90610a series 49 3. dc characteristics (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40c to +85c) *1: hysteresis input pins: rst , hst , p60 to p67, p70 to p76, p80 to p86, p90 to p95, pa1 to pa7 *2: ttl input pins: ad00/d00 to ad07/d07, ad08/d08/p10 to ad15/d15/p17, hrq/p53, rdy/p51 parameter symbol pin name conditions value unit remarks min. typ. max. h level input voltage v ih 0.7 v cc v cc + 0.3 v v ihs 0.8 v cc v cc + 0.3 v *1 v ihm v cc C 0.3 v cc + 0.3 v v iht v cc = +5.0 v10% 2.2 v *2 v cc = +3.0 v10% 0.7 v cc v*2 l level input voltage v il v ss C 0.3 0.3 v cc v v ils v ss C 0.3 0.2 v cc v*1 v ilm v ss C 0.3 v ss + 0.3 v v ilt v cc = +5.0 v10% v ss C 0.3 0.8 v *2 v cc = +3.0 v10% v ss C 0.3 0.2 v cc v*2 h level output voltage v oh other than p60 to p67 v cc = +5.0 v10% i oh = C4.0 ma v cc C 0.5 v v cc = +3.0 v10% i oh = C1.6 ma v cc C 0.3 v l level output voltage v ol all output pins v cc = +5.0 v10% i ol = C4.0 ma 0.4v v cc = +3.0 v10% i ol = C2.0 ma 0.4v pull-up resistance r pu rst , p50 to p55, rd , ale, pa 1 t o pa 7 , cs0 30100k w supply current i cc v cc v cc = +5.0 v10% 16 mhz internal operation 5070ma i ccs 2530ma i cc v cc = +3.0 v10% 8 mhz internal operation 1020ma i ccs 510ma i cch v cc = +5.0 v10% t a = 25c 0.110 m a input pin capacitance c in other than av cc , av ss , v cc ,v ss 10pf input leakage current i il other than p60 to p67 v cc = 5.5 v v ss < v i < v cc C10 10 m a leakage current for open drain outputs i leak other than p60 to p67 0.110 m a pull-down resistance r pd md2 40 200 k w
50 mb90610a series 4. ac characteristics (1) clock timing ?when v cc = +5.0 v10% (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40c to +85c) * : the frequency variation ratio is the maximum variation from the specified central frequency when the multiplier pll is locked. the value is expressed as a proportion. ?when v cc = +2.7 v (min.) (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40c to +85c) parameter sym- bol pin name conditions value unit remarks min. max. clock frequency f c x0, x1 3 32 mhz clock cycle time t c x0, x1 31.25 333 ns frequency variation ratio* (when locked) d f 3% input clock pulse width p wh p wl x0 10 ns the duty ratio should be in the range 30 to 70% input clock rise time and fall time t cr t cf x0 5 ns internal operating clock frequency f cp 1.516mhz internal operating clock cycle time t cp 62.5666ns parameter sym- bol pin name conditions value unit remarks min. max. clock frequency f c x0, x1 3 16 mhz clock cycle time t c x0, x1 62.5 333 ns input clock pulse width p wh p wl x0 20 ns the duty ratio should be in the range 30 to 70% input clock rise time and fall time t cr t cf x0 5 ns internal operating clock frequency f cp 1.58mhz internal operating clock cycle time t cp 125 666 ns d f = 100 (%) f 0 central frequency f 0 + a - a a
mb90610a series 51 0.8 v cc 0.2 v cc t c t cf t cr p wh p wl ? clock timing 5.5 4.5 2.7 816 f cp (mhz) normal operation range 3.3 3 1.5 pll operation assurance range internal clock 34 8 16 24 32 16 12 9 8 4 multiply by 3 multiply by 4 no multiplier oscillation clock f c (mhz) relationship between the oscillation frequency and internal operating clock frequency relationship between the internal operating clock frequency and supply voltage multiply by 1 multiply by 2 note: low voltage operation down to 2.7v is also assured for the evaluation tools. power supply v cc (v) internal clock f cp (mhz) ? pll operation assurance range
52 mb90610a series the ac characteristics are for the following measurement reference voltages. (2) clock output timing (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40c to +85c) parameter sym- bol pin name conditions value unit remarks min. max. cycle time t cyc clk v cc = +5 v10% t cp ns clk - ? clk t chcl t cp /2 C 20 t cp /2 + 20 ns hysteresis input pins 0.8 v cc 0.2 v cc other than hysteresis/md input pins 0.7 v cc 0.3 v cc output pins 2.4 v 0.8 v ? input signal waveform ? output signal waveform t cyc t chcl clk 0.8 v 2.4 v 2.4 v
mb90610a series 53 (3) recommended resonator manufacturers x0 x1 c1 c2 *2 *2 far *1: fujitsu acoustic resonator *1 r inquiry: fujitsu limited far part number (built-in capacitor type) frequency (mhz) dumping resistor initial deviation of far frequency (t a = +25 c) temperature characteristics of far frequency (t a = C20 c to +60 c) loading capacitors* 2 far-c4cc-02000-l20 2.00 1 k w 0.5% 0.5% built-in far-c4ca-04000-m01 4.00 0.5% 0.5% far-c4cb-08000-m02 8.00 0.5% 0.5% far-c4cb-10000-m02 10.00 0.5% 0.5% far-c4cb-16000-m02 16.00 0.5% 0.5% ? sample application of piezoelectric resonator (far family)
54 mb90610a series (continued) x0 x1 c1 c2 *3 *2 *1 r *4 ? sample application of ceramic resonator resonator manufacturer* 1 resonator frequency (mhz) c1 (pf)* 2 c2 (pf)* 3 r* 4 kyocera corporation kbr-2.0ms 2.00 150 150 not required pbrc2.00a 150 150 not required kbr-4.0msa 4.00 33 33 680 w kbr-4.0mks built-in built-in 680 w pbrc4.00a 33 33 680 w pbrc4.00b built-in built-in 680 w kbr-6.0msa 6.00 33 33 not required kbr-6.0mks built-in built-in not required pbrc6.00a 33 33 not required pbrc6.00b built-in built-in not required kbr-8.0m 8.00 33 33 560 w pbrc8.00a 33 33 not required pbrc8.00b built-in built-in not required kbr-10.0m 10.00 33 33 330 w pbrc10.00b built-in built-in 680 w kbr-12.0m 12.00 33 33 330 w pbrc12.00b built-in built-in 680 w
mb90610a series 55 (continued) inquiry: kyocera corporation avx corporation north american sales headquarters: tel 1-803-448-9411 avx limited european sales headquarters: tel 44-1252-770000 avx/kyocera h.k. ltd. asian sales headquarters: tel 852-363-3303 murata mfg. co., ltd. murata electronics north america, inc.: tel 1-404-436-1300 murata europe management gmbh: tel 49-911-66870 murata electronics singapore (pte.) ltd.: tel 65-758-4233 resonator manufacturer* 1 resonator frequency (mhz) c1 (pf)* 2 c2 (pf)* 3 r* 4 murata mfg. co., ltd. csa2.00mg040 2.00 100 100 not required cst2.00mg040 built-in built-in not required csa4.00mg040 4.00 100 100 not required cst4.00mgw040 built-in built-in not required csa6.00mg 6.00 30 30 not required cst6.00mgw built-in built-in not required csa8.00mtz 8.00 30 30 not required cst8.00mtw built-in built-in not required csa10.00mtz 10.00 30 30 not required cst10.00mtw built-in built-in not required csa12.00mtz 12.00 30 30 not required cst12.00mtw built-in built-in not required csa16.00mxz040 16.00 15 15 not required cst16.00mxw0c3 built-in built-in not required csa20.00mxz040 20.00 10 10 not required csa24.00mxz040 24.00 5 5 not required csa32.00mxz040 32.00 5 5 not required
56 mb90610a series (4) reset and hardware standby inputs (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40c to +85c) parameter sym- bol pin name conditions value unit remarks min. max. reset input time t rstl rst 16 t cp ns hardware standby input time t hstl hst 16 t cp ns rst hst 0.2 v cc 0.2 v cc t rstl , t hstl c l pin c l : load capacity during testing for clk and ale, c l = 30 pf. for address and data buses (ad15 to ad00), rd and wr, c l = 80 pf. ? conditions for measurement of ac reference
mb90610a series 57 (5) power-on reset (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40c to +85c) * : v cc should be lower than 0.2 v before power supply rise. notes: ? the above values are the values required for a power-on reset ? when hst = l, this standard must be followed to turn on power supply for power-on reset whether or not necessary. ? the device has built-in registers which are initialized only by power-on reset. for possible initialization of these registers, turn on power supply according to this standard. parameter sym- bol pin name conditions value unit remarks min. max. power supply rise time t r v cc 30ms* power supply cut-off time t off v cc 1ms for repetition of the operation 2.7 v t r 0.2 v 0.2 v v cc main power supply voltage sub power supply voltage v ss the gradient should be no more than 50mv/ms. abrupt changes in the power supply voltage may cause a power-on reset. when changing the power supply voltage during operation, the change should be as smooth as possible, as shown in the following figure. t off
58 mb90610a series (6) bus timing (read) (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40c to +85c) parameter sym- bol pin name conditions value unit remarks min. max. ale pulse width t lhll ale v cc = +5.0 v10% t cp /2 C 20 ns v cc = +3.0 v10% t cp /2 C 35 ns valid address ? ale time t avll address v cc = +5.0 v10% t cp /2 C 20 ns v cc = +3.0 v10% t cp /2 C 40 ns ale ? address valid time t llax address t cp /2 C 15 ns valid address ? rd time t avrl rd , address t cp C 15 ns valid address ? valid data input t avdv address/ data v cc = +5.0 v10% 5 t cp /2 C 60 ns v cc = +3.0 v10% 5 t cp /2 C 80 ns rd pulse width t rlrh rd 3 t cp /2 C 20 ns rd ? valid data input t rldv data v cc = +5.0 v10% 3 t cp /2 C 60 ns v cc = +3.0 v10% 3 t cp /2 C 80 ns rd - ? data hold time t rhdx 0ns rd - ? ale - time t rhlh rd , ale t cp /2 C 15 ns rd - ? address valid time t rhax address, rd t cp /2 C 10 ns valid address ? clk - time t avch address, clk t cp /2 C 20 ns rd ? clk - time t rlch rd , clk t cp /2 C 20 ns
mb90610a series 59 clk ale rd address read data t lhll t avrl t rlrh t rhax t rhdx 2.4 v 2.4 v 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 2.2 v 2.2 v 0.8 v a23 to a16 d15 to d00 multiplex mode 0.8 v read data t rhax t rhdx t avdv t rldv 0.8 v 2.4 v 0.8 v 2.4 v 2.2 v 2.2 v 0.8 v a23 to a00 non-multiplex mode 0.8 v 0.8 v 2.4 v t avch t rlch t avll t llax t rhlh t avdv t rldv t avdv
60 mb90610a series (7) bus timing (write) (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40c to +85c) parameter sym- bol pin name conditions value unit remarks min. max. valid address ? wr time t avwl address t cp C 15 ns wr pulse width t wlwh wrl , wrh 3 t cp /2 C 20 ns valid data output ? wr - time t dvwh data 3 t cp /2 C 20 ns wr - ? data hold time t whdx v cc = +5.0 v10% 20 ns v cc = +3.0 v10% 30 ns wr - ? address valid time t whax address t cp /2 C 10 ns wr - ? ale - time t whlh ale, wrl , wrh t cp /2 C 15 ns wr ? clk time t wlcl wrl , wrh , clk t cp /2 C 20 ns clk ale wr (wrl, wrh) address write data t whdx t whax t wlwh t avwl 0.8 v 2.4 v a23 to a16 ad15 to ad00 2.4 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v multiplex mode write data t whdx a23 to a00 d15 to d00 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v non-multiplex mode t wlch t whlh t whdx t whax t dvwh t dvwh
mb90610a series 61 (8) ready input timing (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40c to +85c) note: use the auto-ready function if the setup time at fall of the rdy is too short. parameter sym- bol pin name conditions value unit remarks min. max. rdy setup time t ryhs rdy v cc = +5.0 v10% 45 ns v cc = +3.0 v10% 70 ns rdy hold time t ryhh rdy 0 ns clk ale rdy (wait cycle) rdy (no wait cycle) rd/wr 2.4 v 2.4 v t ryhs t ryhs t ryhs t ryhh 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc
62 mb90610a series (9) hold timing (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40c to +85c) note: after reading hrq, more than one cycle is required before changing hak . parameter sym- bol pin name conditions value unit remarks min. max. pin floating ? hak time t xhal hak 30t cp ns hak - ? pin valid time t hahv hak t cp 2 t cp ns hrq high impedance hak pin 0.8 v 2.4 v t xhal t hahv
mb90610a series 63 (10) i/o expansion serial timing (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40c to +85c) notes: ? these are the ac characteristics for clk synchronous mode. ?c l is the load capacitance connected to the pin at testing. ?t cp is the machine cycle period (unit: ns). parameter sym- bol pin name conditions value unit remarks min. max. serial clock cycle time t scyc sck0 to 2 8 t cp ns c l = 80 pf + 1 ttl for the internal shift clock mode output pin. sck ? sot delay time t slov sck0 to 2 sot0 to 2 v cc = +5.0 v10% C80 80 ns v cc = +3.0 v10% C120 120 ns valid sin ? sck - t ivsh sck0 to 2 sin0 to 2 v cc = +5.0 v10% 100 ns v cc = +3.0 v10% 200 ns sck - ? valid sin hold time t shix sck0 to 2 sin0 to 2 v cc = +5.0 v10% 60 ns v cc = +3.0 v10% 120 ns serial clock h pulse width t shsl sck0 to 2 4 t cp ns c l = 80 pf + 1 ttl for the external shift clock mode output pin. serial clock l pulse width t slsh sck0 to 2 4 t cp ns sck ? sot delay time t slov sck0 to 2 sot0 to 2 v cc = +5.0 v10% 150 ns v cc = +3.0 v10% 200 ns valid sin ? sck - t ivsh sck0 to 2 sin0 to 2 v cc = +5.0 v10% 60 ns v cc = +3.0 v10% 120 ns sck - ? valid sin hold time t shix sck0 to 2 sin0 to 2 v cc = +5.0 v10% 60 ns v cc = +3.0 v10% 120 ns
64 mb90610a series sck sot sin t scyc t slov t ivsh t shix 2.4 v 0.8 v cc 0.8 v 0.8 v 2.4 v 0.8 v 0.2 v cc 0.8 v cc 0.2 v cc sck sot sin t slsh t slov t ivsh t shix t shsl 0.8 v cc 2.4 v 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc ? internal shift clock mode ? external shift clock mode
mb90610a series 65 (11) timer input timing (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40c to +85c) (12) timer output timing (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40c to +85c) parameter sym- bol pin name conditions value unit remarks min. max. input pulse width t tiwh/l tin0 to 1 4 t cp ns parameter sym- bol pin name conditions value unit remarks min. max. clk - ? t out change timing t to tot0 to 1 v cc = +5.0 v10% 30 ns v cc = +3.0 v10% 80 ns 0.8 v cc 0.2 v cc t tiwh 0.2 v cc 0.8 v cc t tiwl ? timer input timing clk t out t to 2.4 v cc 2.4 v 0.8 v cc ? timer output timing
66 mb90610a series (13) trigger input timing (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40c to +85c) (14) chip select output timing (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40c to +85c) parameter sym- bol pin name conditions value unit remarks min. max. input pulse width t trgh t trgl at g int0 to int1 5 t cp ns parameter sym- bol pin name conditions value unit remarks min. max. chip select enabled ? valid data input time t svdv cs0 to cs7 d15 to d00 v cc = +5.0 v10% 5 t cp /2 C 60 ns v cc = +3.0 v10% 5 t cp /2 C 80 ns rd - ? chip select enabled time t rhsv cs0 to cs7 rd t cp /2 C 10 ns wr - ? chip select enabled time t whsv cs0 to cs7 wrh , wrl t cp /2 C 10 ns enabled chip select ? clk - time t svch cs0 to cs7 clk t cp /2 C 20 ns 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t trgh t trgl
mb90610a series 67 clk rd read data t svch 2.4 v a23 to a00 cs0 to cs7 d15 to d00 2.4 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v write data wr (wrl, wrh) d15 to d00 t rhsv t whsv t svdv
68 mb90610a series 5. a/d converter electrical characteristics (av cc = v cc = +2.7 v to +5.5 v, av ss = v ss = 0.0 v, 2.7 v avrh C avrl, t a = C40c to +85c) *1: for v cc = +5.0 v10% and a 16 mhz machine clock *2: for v cc = +3.0 v10% and a 8 mhz machine clock *3: the current when the a/d converter is not operating or the cpu is in stop mode (for v cc = av cc = avrh = +5.0 v). notes: ? the relative error increases as |avrh C avrl| decreases. ? the output impedance of the external circuit for the analog input should be in the following range. output impedance of external circuit < approx. 7 k w ? if the output impedance of the external circuit is too high, the sampling time for the analog voltage may be too short. (sampling time = 3.75 m s @4 mhz (this corresponds to 16 mhz internal operation if the multiplier is 4.)) ? for an external capacitor to be provided outside the chip, its capacity should desirably be thousands times larger than that of the capacity in the chip taking in consideration the influence of the capacity distribution of the external and internal capacitors. parameter symbol pin name value unit min. typ. max. resolution 10 10 bit total error 3.0 lsb linearity error 2.0 lsb differential linearity error 1.5 lsb zero transition voltage v ot an0 to an7 avrl C 1.5 avrl + 0.5 avrl + 2.5 lsb full scale transition voltage v fst an0 to an7 avrh C 4.5 avrh C 1.5 avrh + 0.5 lsb conversion time 6.125* 1 m s 12.25* 2 m s analog port input current i ain an0 to an7 0.110 m a analog input voltage v ain an0 to an7 avrl avrh v reference voltage avrh avrl + 2.7 av cc v avrl 0 avrh C 2.7 v power supply current i a av cc 3ma i ah av cc 5 *3 m a reference voltage supply current i r avrh 200 m a i rh avrh 5 *3 m a variation between channels an0 to an7 4lsb
mb90610a series 69 6. a/d converter glossary ? resolution the change in analog voltage that can be recognized by the a/d converter. if the resolution is 10 bits, the analog voltage can be resolved into 2 10 = 1024 steps. ? total error the deviation between the actual and logic value attributable to offset error, gain error, non-linearity error, and noise. ? linearity error the deviation between the actual conversion characteristic of the device and the line linking the zero transition point (00 0000 0000 ? 00 0000 0001) and the full scale transition point (11 1111 1110 ? 11 1111 1111). ? differential linearity error the variation from the ideal input voltage required to change the output code by 1 lsb. comparator analog input r on1 r on2 c 1 c 0 r on1 = 1.5 k w (approx.) (v cc = 5.0 v) r on2 = 0.5 k w (approx.) (v cc = 5.0 v) r on3 = 0.5 k w (approx.) (v cc = 5.0 v) r on4 = 0.5 k w (approx.) (v cc = 5.0 v) c 0 = 60 pf (approx.) c 1 = 4 pf (approx.) r on3 r on4 sample and hold circuit note: the above values are for reference only. ? model of the analog input circuit digital output 1111 1111 1111 1110 0000 0001 0000 0000 0000 0010 v ot v nt v (n + 1)t v fst (1 lsb n + v ot ) analog input linearity error 1 lsb = 1022 v fst ?v ot linearity error = 1 lsb v nt ?(1 lsb n + v ot ) (lsb) 11 11 00 00 00 1 lsb v (n + 1)t ?v nt ?1 (lsb) differential linearity error =
70 mb90610a series n examples characteristics v cc = 5.0 v v cc = 4.5 v i oh (ma) ? 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 v oh ?i oh ? ? ? v cc = 4.0 v v cc = 3.0 v v cc = 2.7 v v cc = 3.5 v t a = +25? v oh (v) v cc = 5.0 v v ol (v) v cc = 4.5 v i ol (ma) 8 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 v ol ?i ol 46 2 v cc = 4.0 v v cc = 3.0 v v cc = 2.7 v v cc = 3.5 v t a = +25? 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 v in (v) v cc (v) 23 456 t a = +25? v in ?v cc (cmos input) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 v in (v) v cc (v) 23 456 t a = +25? v in ?v cc (hysteresis input) v ihs v ils v ihs : threshold when input voltage in hysteresis characteristics is set to h level v ils : threshold when input voltage in hysteresis characteristics is set to l level (3) h level input voltage/l level input voltage (4) h level input voltage/l level input voltage (1) h level output voltage (2) l level output voltage
mb90610a series 71 (5) power supply current (fcp = internal frequency) (6) pull-up resistance i cc (ma) i cc ?v cc 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 3.0 4.0 5.0 6.0 v cc (v) f cp = 16 mhz f cp = 12.5 mhz f cp = 8 mhz f cp = 4 mhz t a = +25? i ccs (ma) i ccs ?v cc 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3.0 4.0 5.0 6.0 v cc (v) f cp = 16 mhz f cp = 12.5 mhz f cp = 8 mhz f cp = 4 mhz t a = +25? i a (ma) i a ?av cc 3.0 4.0 5.0 6.0 av cc (v) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 t a = +25? f cp = 16 mhz i r (ma) i r ?avr 3.0 4.0 5.0 6.0 avr (v) 0.30 0.20 0.10 0 t a = +25? f cp = 16 mhz 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1000 r (k ) v cc (v) 100 10 2.5 t a = +25? r ?v cc
72 mb90610a series n instructions (340 instructions) table 1 explanation of items in tables of instructions item meaning mnemonic upper-case letters and symbols: represented as they appear in assembler. lower-case letters: replaced when described in assembler. numbers after lower-case letters: indicate the bit width within the instruction. # indicates the number of bytes. ~ indicates the number of cycles. m : when branching n : when not branching see table 4 for details about meanings of other letters in items. rg indicates the number of accesses to the register during execution of the instruction. it is used calculate a correction value for intermittent operation of cpu. b indicates the correction value for calculating the number of actual cycles during execution of the instruction. (table 5) the number of actual cycles during execution of the instruction is the correction value summed with the value in the ~ column. operation indicates the operation of instruction. lh indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator. z : transfers 0. x : extends with a sign before transferring. C : transfers nothing. ah indicates special operations involving the upper 16 bits in the accumulator. * : transfers from al to ah. C : no transfer. z : transfers 00 h to ah. x : transfers 00 h or ff h to ah by signing and extending al. i indicates the status of each of the following flags: i (interrupt enable), s (stack), t (sticky bit), n (negative), z (zero), v (overflow), and c (carry). * : changes due to execution of instruction. C : no change. s : set by execution of instruction. r : reset by execution of instruction. s t n z v c rmw indicates whether the instruction is a read-modify-write instruction. (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.) * : instruction is a read-modify-write instruction. C : instruction is not a read-modify-write instruction. note: a read-modify-write instruction cannot be used on addresses that have different meanings depending on whether they are read or written.
mb90610a series 73 table 2 explanation of symbols in tables of instructions (continued) symbol meaning a 32-bit accumulator the bit length varies according to the instruction. byte : lower 8 bits of al word : 16 bits of al long : 32 bits of al:ah ah al upper 16 bits of a lower 16 bits of a sp stack pointer (usp or ssp) pc program counter pcb program bank register dtb data bank register adb additional data bank register ssb system stack bank register usb user stack bank register spb current stack bank register (ssb or usb) dpr direct page register brg1 dtb, adb, ssb, usb, dpr, pcb, spb brg2 dtb, adb, ssb, usb, dpr, spb ri r0, r1, r2, r3, r4, r5, r6, r7 rwi rw0, rw1, rw2, rw3, rw4, rw5, rw6, rw7 rwj rw0, rw1, rw2, rw3 rli rl0, rl1, rl2, rl3 dir compact direct addressing addr16 addr24 ad24 0 to 15 ad24 16 to 23 direct addressing physical direct addressing bit 0 to bit 15 of addr24 bit 16 to bit 23 of addr24 io i/o area (000000 h to 0000ff h ) imm4 imm8 imm16 imm32 ext (imm8) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data disp8 disp16 8-bit displacement 16-bit displacement bp bit offset vct4 vct8 vector number (0 to 15) vector number (0 to 255) ( )b bit address
74 mb90610a series (continued) table 3 effective address fields note: the number of bytes in the address extension is indicated by the + symbol in the # (number of bytes) column in the tables of instructions. symbol meaning rel branch specification relative to pc ear eam effective addressing (codes 00 to 07) effective addressing (codes 08 to 1f) rlst register list code notation address format number of bytes in address extension * 00 01 02 03 04 05 06 07 r0 r1 r2 r3 r4 r5 r6 r7 rw0 rw1 rw2 rw3 rw4 rw5 rw6 rw7 rl0 (rl0) rl1 (rl1) rl2 (rl2) rl3 (rl3) register direct ea corresponds to byte, word, and long-word types, starting from the left 08 09 0a 0b @rw0 @rw1 @rw2 @rw3 register indirect 0 0c 0d 0e 0f @rw0 + @rw1 + @rw2 + @rw3 + register indirect with post-increment 0 10 11 12 13 14 15 16 17 @rw0 + disp8 @rw1 + disp8 @rw2 + disp8 @rw3 + disp8 @rw4 + disp8 @rw5 + disp8 @rw6 + disp8 @rw7 + disp8 register indirect with 8-bit displacement 1 18 19 1a 1b @rw0 + disp16 @rw1 + disp16 @rw2 + disp16 @rw3 + disp16 register indirect with 16-bit displacement 2 1c 1d 1e 1f @rw0 + rw7 @rw1 + rw7 @pc + disp16 addr16 register indirect with index register indirect with index pc indirect with 16-bit displacement direct address 0 0 2 2
mb90610a series 75 table 4 number of execution cycles for each type of addressing note: (a) is used in the ~ (number of states) column and column b (correction value) in the tables of instructions. table 5 correction values for number of cycles used to calculate number of actual cycles notes: (b), (c), and (d) are used in the ~ (number of states) column and column b (correction value) in the tables of instructions. when the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. table 6 correction values for number of cycles used to calculate number of program fetch cycles notes: when the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. because instruction execution is not slowed down by all program fetches in actuality, these correction values should be used for worst case calculations. code operand (a) number of register accesses for each type of addressing number of execution cycles for each type of addressing 00 to 07 ri rwi rli listed in tables of instructions listed in tables of instructions 08 to 0b @rwj 2 1 0c to 0f @rwj + 4 2 10 to 17 @rwi + disp8 2 1 18 to 1b @rwj + disp16 2 1 1c 1d 1e 1f @rw0 + rw7 @rw1 + rw7 @pc + disp16 addr16 4 4 2 1 2 2 0 0 operand (b) byte (c) word (d) long number of cycles number of access number of cycles number of access number of cycles number of access internal register +01+01+02 internal memory even address internal memory odd address +0 +0 1 1 +0 +2 1 2 +0 +4 2 4 even address on external data bus (16 bits) odd address on external data bus (16 bits) +1 +1 1 1 +1 +4 1 2 +2 +8 2 4 external data bus (8 bits) +11+42+84 instruction byte boundary word boundary internal memory +2 external data bus (16 bits) +3 external data bus (8 bits) +3
76 mb90610a series table 7 transfer instructions (byte) [41 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw mov a, dir mov a, addr16 mov a, ri mov a, ear mov a, eam mov a, io mov a, #imm8 mov a, @a mov a, @rli+disp8 movn a, #imm4 movx a, dir movx a, addr16 movx a, ri movx a, ear movx a, eam movx a, io movx a, #imm8 movx a, @a movx a,@rwi+disp8 movx a, @rli+disp8 mov dir, a mov addr16, a mov ri, a mov ear, a mov eam, a mov io, a mov @rli+disp8, a mov ri, ear mov ri, eam mov ear, ri mov eam, ri mov ri, #imm8 mov io, #imm8 mov dir, #imm8 mov ear, #imm8 mov eam, #imm8 mov @al, ah /mov @a, t xch a, ear xch a, eam xch ri, ear xch ri, eam 2 3 1 2 2+ 2 2 2 3 1 2 3 2 2 2+ 2 2 2 2 3 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 2 2+ 2 2+ 3 4 2 2 3+ (a) 3 2 3 10 1 3 4 2 2 3+ (a) 3 2 3 5 10 3 4 2 2 3+ (a) 3 10 3 4+ (a) 4 5+ (a) 2 5 5 2 4+ (a) 3 4 5+ (a) 7 9+ (a) 0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2 (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2 (b) 0 2 (b) byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? imm8 byte (a) ? ((a)) byte (a) ? ((rli)+disp8) byte (a) ? imm4 byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? imm8 byte (a) ? ((a)) byte (a) ? ((rwi)+disp8) byte (a) ? ((rli)+disp8) byte (dir) ? (a) byte (addr16) ? (a) byte (ri) ? (a) byte (ear) ? (a) byte (eam) ? (a) byte (io) ? (a) byte ((rli) +disp8) ? (a) byte (ri) ? (ear) byte (ri) ? (eam) byte (ear) ? (ri) byte (eam) ? (ri) byte (ri) ? imm8 byte (io) ? imm8 byte (dir) ? imm8 byte (ear) ? imm8 byte (eam) ? imm8 byte ((a)) ? (ah) byte (a) ? (ear) byte (a) ? (eam) byte (ri) ? (ear) byte (ri) ? (eam) z z z z z z z z z z x x x x x x x x x x C C C C C C C C C C C C C C C C C z z C C * * * * * * * C * * * * * * * * * C * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * r * * * * * * * * * * * * * * * * * * * * * * C C * C * C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C * C * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
mb90610a series 77 table 8 transfer instructions (word/long word) [38 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw movw a, dir movw a, addr16 movw a, sp movw a, rwi movw a, ear movw a, eam movw a, io movw a, @a movw a, #imm16 movw a, @rwi+disp8 movw a, @rli+disp8 movw dir, a movw addr16, a movw sp, a movw rwi, a movw ear, a movw eam, a movw io, a movw @rwi+disp8, a movw @rli+disp8, a movw rwi, ear movw rwi, eam movw ear, rwi movw eam, rwi movw rwi, #imm16 movw io, #imm16 movw ear, #imm16 movw eam, #imm16 movw al, ah /movw @a, t xchw a, ear xchw a, eam xchw rwi, ear xchw rwi, eam 2 3 1 1 2 2+ 2 2 3 2 3 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 2 2+ 2 2+ 3 4 1 2 2 3+ (a) 3 3 2 5 10 3 4 1 2 2 3+ (a) 3 5 10 3 4+ (a) 4 5+ (a) 2 5 2 4+ (a) 3 4 5+ (a) 7 9+ (a) 0 0 0 1 1 0 0 0 0 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0 2 0 4 2 (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) (0) (c) 0 (c) 0 (c) 0 (c) (c) 0 2 (c) 0 2 (c) word (a) ? (dir) word (a) ? (addr16) word (a) ? (sp) word (a) ? (rwi) word (a) ? (ear) word (a) ? (eam) word (a) ? (io) word (a) ? ((a)) word (a) ? imm16 word (a) ? ((rwi) +disp8) word (a) ? ((rli) +disp8) word (dir) ? (a) word (addr16) ? (a) word (sp) ? (a) word (rwi) ? (a) word (ear) ? (a) word (eam) ? (a) word (io) ? (a) word ((rwi) +disp8) ? (a) word ((rli) +disp8) ? (a) word (rwi) ? (ear) word (rwi) ? (eam) word (ear) ? (rwi) word (eam) ? (rwi) word (rwi) ? imm16 word (io) ? imm16 word (ear) ? imm16 word (eam) ? imm16 word ((a)) ? (ah) word (a) ? (ear) word (a) ? (eam) word (rwi) ? (ear) word (rwi) ? (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * C * C * C C C C * * * * * * * * * * * * * * * * * * * * * * * * * C * C * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C movl a, ear movl a, eam movl a, #imm32 movl ear, a movl eam, a 2 2+ 5 2 2+ 4 5+ (a) 3 4 5+ (a) 2 0 0 2 0 0 (d) 0 0 (d) long (a) ? (ear) long (a) ? (eam) long (a) ? imm32 long (ear) ? (a) long (eam) ? (a) C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * C C C C C C C C C C C C C C C
78 mb90610a series table 9 addition and subtraction instructions (byte/word/long word) [42 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw add a,#imm8 add a, dir add a, ear add a, eam add ear, a add eam, a addc a addc a, ear addc a, eam adddc a sub a, #imm8 sub a, dir sub a, ear sub a, eam sub ear, a sub eam, a subc a subc a, ear subc a, eam subdc a 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 2 5 3 4+(a) 3 5+(a) 2 3 4+(a) 3 2 5 3 4+(a) 3 5+(a) 2 3 4+(a) 3 0 0 1 0 2 0 0 1 0 0 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2 b) 0 0 (b) 0 0 (b) 0 (b) 0 2 (b) 0 0 (b) 0 byte (a) ? (a) +imm8 byte (a) ? (a) +(dir) byte (a) ? (a) +(ear) byte (a) ? (a) +(eam) byte (ear) ? (ear) + (a) byte (eam) ? (eam) + (a) byte (a) ? (ah) + (al) + (c) byte (a) ? (a) + (ear) + (c) byte (a) ? (a) + (eam) + (c) byte (a) ? (ah) + (al) + (c) (decimal) byte (a) ? (a) Cimm8 byte (a) ? (a) C (dir) byte (a) ? (a) C (ear) byte (a) ? (a) C (eam) byte (ear) ? (ear) C (a) byte (eam) ? (eam) C (a) byte (a) ? (ah) C (al) C (c) byte (a) ? (a) C (ear) C (c) byte (a) ? (a) C (eam) C (c) byte (a) ? (ah) C (al) C (c) (decimal) z z z z C z z z z z z z z z C C z z z z C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C C C C * C C C C C C C C C * C C C C addw a addw a, ear addw a, eam addw a, #imm16 addw ear, a addw eam, a addcw a, ear addcw a, eam subw a subw a, ear subw a, eam subw a, #imm16 subw ear, a subw eam, a subcw a, ear subcw a, eam 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 3 4+(a) 2 3 5+(a) 3 4+(a) 2 3 4+(a) 2 3 5+(a) 3 4+(a) 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 0 0 (c) 0 0 2 (c) 0 (c) 0 0 (c) 0 0 2 (c) 0 (c) word (a) ? (ah) + (al) word (a) ? (a) +(ear) word (a) ? (a) +(eam) word (a) ? (a) +imm16 word (ear) ? (ear) + (a) word (eam) ? (eam) + (a) word (a) ? (a) + (ear) + (c) word (a) ? (a) + (eam) + (c) word (a) ? (ah) C (al) word (a) ? (a) C (ear) word (a) ? (a) C (eam) word (a) ? (a) Cimm16 word (ear) ? (ear) C (a) word (eam) ? (eam) C (a) word (a) ? (a) C (ear) C (c) word (a) ? (a) C (eam) C (c) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C C C C * C C C C C C C * C C addl a, ear addl a, eam addl a, #imm32 subl a, ear subl a, eam subl a, #imm32 2 2+ 5 2 2+ 5 6 7+(a) 4 6 7+(a) 4 2 0 0 2 0 0 0 (d) 0 0 (d) 0 long (a) ? (a) + (ear) long (a) ? (a) + (eam) long (a) ? (a) +imm32 long (a) ? (a) C (ear) long (a) ? (a) C (eam) long (a) ? (a) Cimm32 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * C C C C C C
mb90610a series 79 table 10 increment and decrement instructions (byte/word/long word) [12 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. table 11 compare instructions (byte/word/long word) [11 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw inc ear inc eam dec ear dec eam 2 2+ 2 2+ 2 5+ (a) 3 5+ (a) 2 0 2 0 0 2 (b) 0 2 (b) byte (ear) ? (ear) +1 byte (eam) ? (eam) +1 byte (ear) ? (ear) C1 byte (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C C * C * incw ear incw eam decw ear decw eam 2 2+ 2 2+ 3 5+ (a) 3 5+ (a) 2 0 2 0 0 2 (c) 0 2 (c) word (ear) ? (ear) +1 word (eam) ? (eam) +1 word (ear) ? (ear) C1 word (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C C * C * incl ear incl eam decl ear decl eam 2 2+ 2 2+ 7 9+ (a) 7 9+ (a) 4 0 4 0 0 2 (d) 0 2 (d) long (ear) ? (ear) +1 long (eam) ? (eam) +1 long (ear) ? (ear) C1 long (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C C * C * mnemonic # ~ rg b operation lh ah i s t n z v c rmw cmp a cmp a, ear cmp a, eam cmp a, #imm8 1 2 2+ 2 1 2 3+ (a) 2 0 1 0 0 0 0 (b) 0 byte (ah) C (al) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? imm8 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * C C C C cmpw a cmpw a, ear cmpw a, eam cmpw a, #imm16 1 2 2+ 3 1 2 3+ (a) 2 0 1 0 0 0 0 (c) 0 word (ah) C (al) word (a) ? (ear) word (a) ? (eam) word (a) ? imm16 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * C C C C cmpl a, ear cmpl a, eam cmpl a, #imm32 2 2+ 5 6 7+ (a) 3 2 0 0 0 (d) 0 word (a) ? (ear) word (a) ? (eam) word (a) ? imm32 C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C
80 mb90610a series table 12 multiplication and division instructions (byte/word/long word) [11 instructions] *1: 3 when the result is zero, 7 when an overflow occurs, and 15 normally. *2: 4 when the result is zero, 8 when an overflow occurs, and 16 normally. *3: 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally. *4: 4 when the result is zero, 7 when an overflow occurs, and 22 normally. *5: 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally. *6: (b) when the result is zero or when an overflow occurs, and 2 (b) normally. *7: (c) when the result is zero or when an overflow occurs, and 2 (c) normally. *8: 3 when byte (ah) is zero, and 7 when byte (ah) is not zero. *9: 4 when byte (ear) is zero, and 8 when byte (ear) is not zero. *10: 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0. *11: 3 when word (ah) is zero, and 11 when word (ah) is not zero. *12: 4 when word (ear) is zero, and 12 when word (ear) is not zero. *13: 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw divu a divu a, ear divu a, eam divuw a, ear divuw a, eam mulu a mulu a, ear mulu a, eam muluw a muluw a, ear muluw a, eam 1 2 2+ 2 2+ 1 2 2+ 1 2 2+ * 1 * 2 * 3 * 4 * 5 * 8 * 9 * 10 * 11 * 12 * 13 0 1 0 1 0 0 1 0 0 1 0 0 0 * 6 0 * 7 0 0 (b) 0 0 (c) word (ah) /byte (al) quotient ? byte (al) remainder ? byte (ah) word (a)/byte (ear) quotient ? byte (a) remainder ? byte (ear) word (a)/byte (eam) quotient ? byte (a) remainder ? byte (eam) long (a)/word (ear) quotient ? word (a) remainder ? word (ear) long (a)/word (eam) quotient ? word (a) remainder ? word (eam) byte (ah) *byte (al) ? word (a) byte (a) *byte (ear) ? word (a) byte (a) *byte (eam) ? word (a) word (ah) *word (al) ? long (a) word (a) *word (ear) ? long (a) word (a) *word (eam) ? long (a) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * C C C C C C * * * * * C C C C C C C C C C C C C C C C C
mb90610a series 81 table 13 logical 1 instructions (byte/word) [39 instructions ] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw and a, #imm8 and a, ear and a, eam and ear, a and eam, a or a, #imm8 or a, ear or a, eam or ear, a or eam, a xor a, #imm8 xor a, ear xor a, eam xor ear, a xor eam, a not a not ear not eam 2 2 2+ 2 2+ 2 2 2+ 2 2+ 2 2 2+ 2 2+ 1 2 2+ 2 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 5+ (a) 2 3 5+ (a) 0 1 0 2 0 0 1 0 2 0 0 1 0 2 0 0 2 0 0 0 (b) 0 2 (b) 0 0 (b) 0 2 (b) 0 0 (b) 0 2 (b) 0 0 2 (b) byte (a) ? (a) and imm8 byte (a) ? (a) and (ear) byte (a) ? (a) and (eam) byte (ear) ? (ear) and (a) byte (eam) ? (eam) and (a) byte (a) ? (a) or imm8 byte (a) ? (a) or (ear) byte (a) ? (a) or (eam) byte (ear) ? (ear) or (a) byte (eam) ? (eam) or (a) byte (a) ? (a) xor imm8 byte (a) ? (a) xor (ear) byte (a) ? (a) xor (eam) byte (ear) ? (ear) xor (a) byte (eam) ? (eam) xor (a) byte (a) ? not (a) byte (ear) ? not (ear) byte (eam) ? not (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r C C C C C C C C C C C C C C C C C C C C C C * C C C C * C C C C * C C * andw a andw a, #imm16 andw a, ear andw a, eam andw ear, a andw eam, a orw a orw a, #imm16 orw a, ear orw a, eam orw ear, a orw eam, a xorw a xorw a, #imm16 xorw a, ear xorw a, eam xorw ear, a xorw eam, a notw a notw ear notw eam 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 2 2+ 2 2 3 4+ (a) 3 5+ (a) 2 2 3 4+ (a) 3 5+ (a) 2 2 3 4+ (a) 3 5+ (a) 2 3 5+ (a) 0 0 1 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 2 0 0 0 0 (c) 0 2 (c) 0 0 0 (c) 0 2 (c) 0 0 0 (c) 0 2 (c) 0 0 2 (c) word (a) ? (ah) and (a) word (a) ? (a) and imm16 word (a) ? (a) and (ear) word (a) ? (a) and (eam) word (ear) ? (ear) and (a) word (eam) ? (eam) and (a) word (a) ? (ah) or (a) word (a) ? (a) or imm16 word (a) ? (a) or (ear) word (a) ? (a) or (eam) word (ear) ? (ear) or (a) word (eam) ? (eam) or (a) word (a) ? (ah) xor (a) word (a) ? (a) xor imm16 word (a) ? (a) xor (ear) word (a) ? (a) xor (eam) word (ear) ? (ear) xor (a) word (eam) ? (eam) xor (a) word (a) ? not (a) word (ear) ? not (ear) word (eam) ? not (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r r r r C C C C C C C C C C C C C C C C C C C C C C C C C C * C C C C C * C C C C C * C C *
82 mb90610a series table 14 logical 2 instructions (long word) [6 instructions] table 15 sign inversion instructions (byte/word) [6 instructions] table 16 normalize instruction (long word) [1 instruction] *1: 4 when the contents of the accumulator are all zeroes, 6 + (r0) in all other cases (shift count). note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw andl a, ear andl a, eam orl a, ear orl a, eam xorl a, ea xorl a, eam 2 2+ 2 2+ 2 2+ 6 7+ (a) 6 7+ (a) 6 7+ (a) 2 0 2 0 2 0 0 (d) 0 (d) 0 (d) long (a) ? (a) and (ear) long (a) ? (a) and (eam) long (a) ? (a) or (ear) long (a) ? (a) or (eam) long (a) ? (a) xor (ear) long (a) ? (a) xor (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * r r r r r r C C C C C C C C C C C C mnemonic # ~ rg b operation lh ah i s t n z v c rmw neg a neg ear neg eam 1 2 2+ 2 3 5+ (a) 0 2 0 0 0 2 (b) byte (a) ? 0 C (a) byte (ear) ? 0 C (ear) byte (eam) ? 0 C (eam) x C C C C C C C C C C C C C C * * * * * * * * * * * * C C * negw a negw ear negw eam 1 2 2+ 2 3 5+ (a) 0 2 0 0 0 2 (c) word (a) ? 0 C (a) word (ear) ? 0 C (ear) word (eam) ? 0 C (eam) C C C C C C C C C C C C C C C * * * * * * * * * * * * C C * mnemonic # ~ rg b operation lh ah i s t n z v c rmw nrml a, r0 2 * 1 1 0 long (a) ? shift until first digit is 1 byte (r0) ? current shift count CCCCCC*CC C
mb90610a series 83 table 17 shift instructions (byte/word/long word) [18 instructions] *1: 6 when r0 is 0, 5 + (r0) in all other cases. *2: 6 when r0 is 0, 6 + (r0) in all other cases. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw rorc a rolc a rorc ear rorc eam rolc ear rolc eam asr a, r0 lsr a, r0 lsl a, r0 2 2 2 2+ 2 2+ 2 2 2 2 2 3 5+(a) 3 5+(a) * 1 * 1 * 1 0 0 2 0 2 0 1 1 1 0 0 0 2 (b) 0 2 (b) 0 0 0 byte (a) ? right rotation with carry byte (a) ? left rotation with carry byte (ear) ? right rotation with carry byte (eam) ? right rotation with carry byte (ear) ? left rotation with carry byte (eam) ? left rotation with carry byte (a) ? arithmetic right barrel shift (a, r0) byte (a) ? logical right barrel shift (a, r0) byte (a) ? logical left barrel shift (a, r0) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * C * * * * * * * * * * * * * * * * * * C C C C C C C C C * * * * * * * * * C C C * C * C C C asrw a lsrw a/shrw a lslw a/shlw a asrw a, r0 lsrw a, r0 lslw a, r0 1 1 1 2 2 2 2 2 2 * 1 * 1 * 1 0 0 0 1 1 1 0 0 0 0 0 0 word (a) ? arithmetic right shift (a, 1 bit) word (a) ? logical right shift (a, 1 bit) word (a) ? logical left shift (a, 1 bit) word (a) ? arithmetic right barrel shift (a, r0) word (a) ? logical right barrel shift (a, r0) word (a) ? logical left barrel shift (a, r0) C C C C C C C C C C C C C C C C C C C C C C C C * * C * * C * r * * * * * * * * * * C C C C C C * * * * * * C C C C C C asrl a, r0 lsrl a, r0 lsll a, r0 2 2 2 * 2 * 2 * 2 1 1 1 0 0 0 long (a) ? arithmetic right shift (a, r0) long (a) ? logical right barrel shift (a, r0) long (a) ? logical left barrel shift (a, r0) C C C C C C C C C C C C * * C * * * * * * C C C * * * C C C
84 mb90610a series table 18 branch 1 instructions [31 instructions] *1: 4 when branching, 3 when not branching. *2: (b) + 3 (c) *3: read (word) branch address. *4: w: save (word) to stack; r: read (word) branch address. *5: save (word) to stack. *6: w: save (long word) to w stack; r: read (long word) r branch address. *7: save (long word) to stack. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel bv rel bnv rel bt rel bnt rel blt rel bge rel ble rel bgt rel bls rel bhi rel bra rel jmp @a jmp addr16 jmp @ear jmp @eam jmpp @ear * 3 jmpp @eam * 3 jmpp addr24 call @ear * 4 call @eam * 4 call addr16 * 5 callv #vct4 * 5 callp @ear * 6 callp @eam * 6 callp addr24 * 7 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4 2 2+ 3 1 2 2+ 4 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 2 3 3 4+(a) 5 6+(a) 4 6 7+(a) 6 7 10 11+(a) 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 1 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 (c) 2 (c) (c) 2 (c) 2 (c) * 2 2 (c) branch when (z) = 1 branch when (z) = 0 branch when (c) = 1 branch when (c) = 0 branch when (n) = 1 branch when (n) = 0 branch when (v) = 1 branch when (v) = 0 branch when (t) = 1 branch when (t) = 0 branch when (v) xor (n) = 1 branch when (v) xor (n) = 0 branch when ((v) xor (n)) or (z) = 1 branch when ((v) xor (n)) or (z) = 0 branch when (c) or (z) = 1 branch when (c) or (z) = 0 branch unconditionally word (pc) ? (a) word (pc) ? addr16 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? (ear), (pcb) ? (ear +2) word (pc) ? (eam), (pcb) ? (eam +2) word (pc) ? ad24 0 to 15, (pcb) ? ad24 16 to 23 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? addr16 vector call instruction word (pc) ? (ear) 0 to 15 (pcb) ? (ear) 16 to 23 word (pc) ? (eam) 0 to 15 (pcb) ? (eam) 16 to 23 word (pc) ? addr0 to 15, (pcb) ? addr16 to 23 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
mb90610a series 85 table 19 branch 2 instructions [19 instructions] *1: 5 when branching, 4 when not branching *2: 13 when branching, 12 when not branching *3: 7 + (a) when branching, 6 + (a) when not branching *4: 8 when branching, 7 when not branching *5: 7 when branching, 6 when not branching *6: 8 + (a) when branching, 7 + (a) when not branching *7: retrieve (word) from stack *8: retrieve (long word) from stack *9: in the cbne/cwbne instruction, do not use the rwj+ addressing mode. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw cbne a, #imm8, rel cwbne a, #imm16, rel cbne ear, #imm8, rel cbne eam, #imm8, rel* 9 cwbne ear, #imm16, rel cwbne eam, #imm16, rel* 9 dbnz ear, rel dbnz eam, rel dwbnz ear, rel dwbnz eam, rel int #vct8 int addr16 intp addr24 int9 reti link #local8 unlink ret * 7 retp * 8 3 4 4 4+ 5 5+ 3 3+ 3 3+ 2 3 4 1 1 2 1 1 1 * 1 * 1 * 2 * 3 * 4 * 3 * 5 * 6 * 5 * 6 20 16 17 20 15 6 5 4 6 0 0 1 0 1 0 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 (b) 0 (c) 0 2 (b) 0 2 (c) 8 (c) 6 (c) 6 (c) 8 (c) 6 (c) (c) (c) (c) (d) branch when byte (a) 1 imm8 branch when word (a) 1 imm16 branch when byte (ear) 1 imm8 branch when byte (eam) 1 imm8 branch when word (ear) 1 imm16 branch when word (eam) 1 imm16 branch when byte (ear) = (ear) C 1, and (ear) 1 0 branch when byte (eam) = (eam) C 1, and (eam) 1 0 branch when word (ear) = (ear) C 1, and (ear) 1 0 branch when word (eam) = (eam) C 1, and (eam) 1 0 software interrupt software interrupt software interrupt software interrupt return from interrupt at constant entry, save old frame pointer to stack, set new frame pointer, and allocate local pointer area at constant entry, retrieve old frame pointer from stack. return from subroutine return from subroutine C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r r r r * C C C C C C C C C C C C C C s s s s * C C C C C C C C C C C C C C C C C C * C C C C * * * * * * * * * * C C C C * C C C C * * * * * * * * * * C C C C * C C C C * * * * * * * * * * C C C C * C C C C * * * * * * C C C C C C C C * C C C C C C C C C C C * C * C C C C C C C C C
86 mb90610a series table 20 other control instructions (byte/word/long word) [36 instructions] *1: pcb, adb, ssb, usb, and spb : 1 state dtb, dpr : 2 states *2: 7 + 3 (pop count) + 2 (last register number to be popped), 7 when rlst = 0 (no transfer register) *3: 29 + (push count) C 3 (last register number to be pushed), 8 when rlst = 0 (no transfer register) *4: pop count (c), or push count (c) *1: pop count or push count. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw pushw a pushw ah pushw ps pushw rlst popw a popw ah popw ps popw rlst jctx @a and ccr, #imm8 or ccr, #imm8 mov rp, #imm8 mov ilm, #imm8 movea rwi, ear movea rwi, eam movea a, ear movea a, eam addsp #imm8 addsp #imm16 mov a, brgl mov brg2, a nop adb dtb pcb spb ncc cmr 1 1 1 2 1 1 1 2 1 2 2 2 2 2 2+ 2 2+ 2 3 2 2 1 1 1 1 1 1 1 4 4 4 * 3 3 3 4 * 2 14 3 3 2 2 3 2+ (a) 1 1+ (a) 3 3 * 1 1 1 1 1 1 1 1 1 0 0 0 * 5 0 0 0 * 5 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) (c) (c) * 4 (c) (c) (c) * 4 6 (c) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 word (sp) ? (sp) C2, ((sp)) ? (a) word (sp) ? (sp) C2, ((sp)) ? (ah) word (sp) ? (sp) C2, ((sp)) ? (ps) (sp) ? (sp) C2n, ((sp)) ? (rlst) word (a) ? ((sp)), (sp) ? ( sp) +2 word (ah) ? ((sp)), (sp) ? ( sp) +2 word (ps) ? ((sp)), (sp) ? ( sp) +2 (rlst) ? ((sp)), (sp) ? (sp) +2n context switch instruction byte (ccr) ? (ccr) and imm8 byte (ccr) ? (ccr) or imm8 byte (rp) ? imm8 byte (ilm) ? imm8 word (rwi) ? ear word (rwi) ? eam word(a) ? ear word (a) ? eam word (sp) ? (sp) +ext (imm8) word (sp) ? (sp) +imm16 byte (a) ? (brgl) byte (brg2) ? (a) no operation prefix code for accessing ad space prefix code for accessing dt space prefix code for accessing pc space prefix code for accessing sp space prefix code for no flag change prefix code for common register bank C C C C C C C C C C C C C C C C C C C z C C C C C C C C C C C C * C C C C C C C C C C * * C C * C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C * * C C C C C C C C C C C C C * C * * * C C C C C C C C * * C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
mb90610a series 87 table 21 bit manipulation instructions [21 instructions] *1: 8 when branching, 7 when not branching *2: 7 when branching, 6 when not branching *3: 10 when condition is satisfied, 9 when not satisfied *4: undefined count *5: until condition is satisfied note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw movb a, dir:bp movb a, addr16:bp movb a, io:bp movb dir:bp, a movb addr16:bp, a movb io:bp, a setb dir:bp setb addr16:bp setb io:bp clrb dir:bp clrb addr16:bp clrb io:bp bbc dir:bp, rel bbc addr16:bp, rel bbc io:bp, rel bbs dir:bp, rel bbs addr16:bp, rel bbs io:bp, rel sbbs addr16:bp, rel wbts io:bp wbtc io:bp 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 5 5 4 7 7 6 7 7 7 7 7 7 * 1 * 1 * 2 * 1 * 1 * 2 * 3 * 4 * 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (b) (b) (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) (b) (b) (b) (b) (b) (b) 2 (b) * 5 * 5 byte (a) ? (dir:bp) b byte (a) ? (addr16:bp) b byte (a) ? (io:bp) b bit (dir:bp) b ? (a) bit (addr16:bp) b ? (a) bit (io:bp) b ? (a) bit (dir:bp) b ? 1 bit (addr16:bp) b ? 1 bit (io:bp) b ? 1 bit (dir:bp) b ? 0 bit (addr16:bp) b ? 0 bit (io:bp) b ? 0 branch when (dir:bp) b = 0 branch when (addr16:bp) b = 0 branch when (io:bp) b = 0 branch when (dir:bp) b = 1 branch when (addr16:bp) b = 1 branch when (io:bp) b = 1 branch when (addr16:bp) b = 1, bit = 1 wait until (io:bp) b = 1 wait until (io:bp) b = 0 z z z C C C C C C C C C C C C C C C C C C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * C C C C C C C C C C C C C C C * * * * * * C C C C C C * * * * * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * C C C C C C * C C
88 mb90610a series table 22 accumulator manipulation instructions (byte/word) [6 instructions] table 23 string instructions [10 instructions] m: rw0 value (counter value) n: loop count *1: 5 when rw0 is 0, 4 + 7 (rw0) for count out, and 7 n + 5 when match occurs *2: 5 when rw0 is 0, 4 + 8 (rw0) in any other case *3: (b) (rw0) + (b) (rw0) when accessing different areas for the source and destination, calculate (b) separately for each. *4: (b) n *5: 2 (rw0) *6: (c) (rw0) + (c) (rw0) when accessing different areas for the source and destination, calculate (c) separately for each. *7: (c) n *8: 2 (rw0) note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw swap swapw/xchw al, ah ext extw zext zextw 1 1 1 1 1 1 3 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 byte (a) 0 to 7 ? (a) 8 to 15 word (ah) ? (al) byte sign extension word sign extension byte zero extension word zero extension C C x C z C C * C x C z C C C C C C C C C C C C C C C C C C C C * * r r C C * * * * C C C C C C C C C C C C C C C C C C mnemonic # ~ rg b operation lh ah i s t n z v c rmw movs/movsi movsd sceq/sceqi sceqd fisl/filsi 2 2 2 2 2 * 2 * 2 * 1 * 1 6m+6 * 5 * 5 * 5 * 5 * 5 * 3 * 3 * 4 * 4 * 3 byte transfer @ah+ ? @al+, counter = rw0 byte transfer @ahC ? @alC, counter = rw0 byte retrieval (@ah+) C al, counter = rw0 byte retrieval (@ahC) C al, counter = rw0 byte filling @ah+ ? al, counter = rw0 C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * C C * * * C C * * C C C * * C C C C C C movsw/movswi movswd scweq/scweqi scweqd filsw/filswi 2 2 2 2 2 * 2 * 2 * 1 * 1 6m+6 * 8 * 8 * 8 * 8 * 8 * 6 * 6 * 7 * 7 * 6 word transfer @ah+ ? @al+, counter = rw0 word transfer @ahC ? @alC, counter = rw0 word retrieval (@ah+) C al, counter = rw0 word retrieval (@ahC) C al, counter = rw0 word filling @ah+ ? al, counter = rw0 C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * C C * * * C C * * C C C * * C C C C C C
mb90610a series 89 n ordering information part number package remarks MB90611APFV 100-pin plastic lqfp (fpt-100p-m05) mb90611apf 100-pin plastic qfp (fpt-100p-m06)
90 mb90610a series n package dimensions (.031.008) 0.800.20 lead no. (.012.004) 0.300.10 0.65(.0256)typ 0.30(.012) 0.25(.010) 100 81 80 51 50 31 30 1 22.300.40(.878.016) 18.85(.742)ref m 0.13(.005) (.705.016) (.551.008) 14.000.20 17.900.40 20.000.20(.787.008) 23.900.40(.941.016) index 0.150.05(.006.002) (stand off) 0.05(.002)min 3.35(.132)max (.642.016) 16.300.40 ref 12.35(.486) details of "b" part 0 10 details of "a" part 0.18(.007)max 0.53(.021)max 0.10(.004) "b" "a" 1994 fujitsu limited f100008-3c-2 c c 1995 fujitsu limited f100007s-2c-3 details of "b" part 16.000.20(.630.008)sq 14.000.10(.551.004)sq 0.50(.0197)typ .007 ?.001 +.003 ?0.03 +0.08 0.18 index 0.10(.004) 0.08(.003) m .059 ?.004 +.008 ?0.10 +0.20 1.50 .005 ?.001 +.002 ?0.02 +0.05 0.127 15.00 12.00 (.472) ref (.591) nom "b" "a" 25 26 1 100 75 51 50 76 0.500.20(.020.008) details of "a" part 0.40(.016)max 0.15(.006)max 0.15(.006) 0.15(.006) 0.100.10 (.004.004) (stand off) 0~10? lead no. (mounting height) dimensions in mm (inches) dimensions in mm (inches) 100-pin plastic qfp (fpt-100p-m06) 100-pin plastic lqfp (fpt-100p-m05)
mb90610a series 91 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: 81(44) 754-3763 fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9907 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.

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